The fundamental operations of the communication are the multiplication and division. The multiplier usually consumes a larger area and power and poses a very high latency. As all the above mentioned characteristics of the multiplier depends on the techniques utilized for the multiplication. It becomes necessary to put into effect a proper multiplier that reduces both the latency and the power consumption. So the paper analysis the performance of the various multipliers and scopes to develop a low power high speed multiplier based on the Baugh Wooley algorithm. The Performance analysis of the Baugh Wooley multiplier and the other existing multipliers is done and was found that the performance of the Baugh Wooley in terms of the latency and the power consumption was convincing compared to the other existing methods.

https://www.irojournals.com/iroei/V1/I2/01.pdf

Design and analysis of low-power, high-speed baugh wooley multiplier

Background/Objectives: Power consumption is one of the important designsin many digital signal processing applications, the main building blocks of the processor is Multiplier-Accumulator (MAC) unit. Methods/Statistical Analysis: In the present work, the Baugh-Wooley multiplier is implemented for improving the performance of MAC unit. The Baugh wooley multiplier is faster than the other multipliers like Array multiplier, Wallace tree multiplier, Booth multiplier. The MAC unit using Baugh-Wooley multiplier is implemented using 180nm technology in cadence virtuoso. Findings: The speed of MAC unit using Wallace tree multiplier is 93.6MHz and with Baugh wooley multiplier is 99.1MHz. The power consumption of the MAC unit using Wallace tree multiplier is 2.265mW and with Baugh wooley multiplier is 4.628mW. The results show that the MAC unit using Baugh wooley multiplier is faster than the Wallace tree multiplier. Application/Improvements: MAC unit processors. In future, we can implement MAC unit using Baugh wooley multiplier with apipelining technique such that the total power consumption will be less.

Comparative Analysis of different Algorithm for Design of High-Speed Multiplier Accumulator Unit (MAC)

\n\n The present study explores a novel self-pipelining strategy that can enhance\nspeed-power efficiency as well as the reliability of a binary multiplier as compared to state-of-art register\nand wavepipelining.\n\n\n\nProper synchronization with efficient clocking between the subsequent self-pipelining stages\nhas been assured to design a self-pipelined multiplier. Each self-pipelining stage consists of self-latching\nleaf cells that are designed, optimized and evaluated by TSMC 0.18μm CMOS technology with 1.8V\nsupply rail and at 25°C temperature. The T-Spice transient response and simulated results for the designed\ncircuits are presented. The proposed idea has been applied to design 4-b×4-b self-pipelined Wallace-\ntree multiplier. The multiplier was validated for all possible test patterns and the transient response\nwas evaluated. The circuit performance in terms of propagation delay, average power and Power-Delay-\nProduct (PDP) is recorded. Next, the decomposition logic is applied to design a higher-order multiplier\n(i.e., 8-bit×8-bit and 16-bit×16-bit) based on the proposed strategy using 4-bit×4-bit self-pipelined multiplier.\nThe designed multiplier was also validated through extensive TSpice simulation for all the required\ntest patterns using W-Edit and the evaluated performance is presented. All the designs, optimizations and\nevaluations performed are based on BSIM3 device parameter of TSMC 0.18μm CMOS technology with\n1.8V supply rail at 25°C temperature using S-Edit of Tanner EDA.\n\n\n\nThe reliability was investigated of the proposed 4-b×4-b multiplier in the temperature range -\n40°C to 100°C for maximum PDP variation.\n\n\n\nA benchmarking analysis in terms of speed-power performance with recent competitive\ndesign reveals preeminence of the proposed technique.\n

Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication

This paper presents a new architecture of energy recycling for low power applications. The reported design is based on the ultra-low-power diode Based on this concept, adiabatic logic inverter, a s...

VLSI implementation of Wave Shaping Diode based Adiabatic Logic (WSDAL)

Dynamic logic families that rely on energy recovery to achieve low energy dissipation control the flow of data through gate cascades using multiphase clocks. Consequently, they typically use multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to their high complexity and clock skew management problems. In this paper, we present TSEL, the first energy-recovering (a.k.a. adiabatic) logic family that operates with a single-phase sinusoidal clocking scheme. We also present SCAL, a source-coupled variant of TSEL with improved supply voltage scalability and energy efficiency. Optimal performance under any operating conditions is achieved in SCAL using a tunable current source in each gate. TSEL and SCAL outperform previous adiabatic logic families in terms of energy efficiency and operating speed. In layout-based simulations with 0.5 μm standard CMOS process parameters, 8-bit carry-lookahead adders (CLAs) in TSEL and SCAL function correctly for operating frequencies exceeding 200 MHz. In comparison with corresponding CLAs in alternative logic styles that operate at minimum supply voltages, CLAs designed in our single-phase adiabatic logic families are more energy efficient across a broad range of operating frequencies. Specifically, for clock rates ranging from 10 to 200 MHz, our 8-bit SCAL CLAs are 1.5 to 2.5 times more energy efficient than corresponding adders developed in PAL and 2N2P and 2.0 to 5.0 times less dissipative than their purely combinational or pipelined CMOS counterparts.

True single-phase adiabatic circuitry

This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180nm technology library files.

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

Background: Multiplication forms one of the most power hungry operations in a digital system. It is used extensively in the digital signal processing applications and in any general purpose processors. Hence, the efficient hardware realization of the multiplier is crucial in ensuring that the processors operate within the power limits and without getting overheated. Method: In order to make the multipliers more power efficient, ways have been found to curtail the spurious glitching in the internal nodes of the multiplier. Latch adder with the delay lines is used in the multiplier to equalize the delay of the partial products. Findings: In this paper, a novel 24 transistor Latch Adder (LA) is proposed. It is validated using the Wallace tree multiplier as a bench marking circuit. Wallace tree multiplier is implemented using the proposed latch adder and delay lines in the internal nodes. Comparison is made with the multipliers constructed using various full adder configurations available in the literature. Conclusion: It is proved that the proposed multiplier circuit achieves the power reduction of 20% compared to the multiplier using 16T full adder. The multiplier is simulated using the industry standard Cadence® Virtuoso tool in 180nm technology library files and the simulation results confirm the low power operation of the multiplier.

A Low Power Multiplier using a 24-Transistor Latch Adder

Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power

https://iopscience.iop.org/article/10.1088/1742-6596/1716/1/012037/pdf

Low power SRAM using Adiabatic Logic

The paper presents the comprehensive analysis and evaluation of static adiabatic logic circuits operated by two phase sinusoidal clock signals. The static adiabatic logic has an advantage in the form of reduction in switching energy while comparing with the dynamic adiabatic logic. This advantage is realized due to the fact that the discharging operation at a node happens only when the input signal transition demands a change in the state of the output. Or in other words, if the next input state happens to be the same as the present state, the charged output nodal state remains the same, without undergoing any recovery phase. The analysis of the static adiabatic logic is done using a carry look ahead adder (CLA) implemented by static adiabatic families, namely, QSERL, CEPAL, ASL and QSECRL and comparing them against the static CMOS counterpart. The performance of each of the circuit is studied in terms of the frequency and power clock voltage range of operation. The simulations show that the 8-bit CLA static adiabatic adder realizes energy reduction from 45% to 83% over a frequency range of 100 KHz to 500MHz operation against the static CMOS implementation. The analyses were carried out using SPICE EDA tools using 180 nm technology library from TSMC.

P. Sasipriya

Papers

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

A Low Power Multiplier using a 24-Transistor Latch Adder

Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power

Low power SRAM using Adiabatic Logic

Two phase sinusoidal power clocked quasi-static adiabatic logic families