Panagiotis Sismanoglou

Bio: Panagiotis Sismanoglou is an academic researcher from University of Patras. The author has contributed to research in topics: Automatic test equipment & Test data. The author has an hindex of 3, co-authored 8 publications receiving 35 citations.

Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches

Abstract: In this paper, we present a new test data compression method for intellectual property (IP) cores testing, based on the reuse of parts of dictionary entries. Two approaches are investigated: the static and the dynamic. In the static approach, the content of the dictionary is constant during the testing of a core, while in the dynamic approach the testing of a core consists of several test sessions and the content of the dictionary is different during each test session. The efficiency of the proposed method is supported with extensive simulation results and comparisons to already known test data compression methods suitable for IP cores testing.

Test data compression based on the reuse of parts of the dictionary entries

Abstract: In this paper we show that the test data compression achieved by a dictionary based method can be improved significantly by suitably reusing parts of the dictionary entries. To this end two new algorithms are proposed, suitable for partial and complete dictionary coding respectively. The efficiency of the proposed techniques is supported with extensive simulation results.

Test data compression based on reuse and bit-flipping of parts of dictionary entries

Abstract: Several dictionary-based input test data compression methods have been proposed for intellectual property (IP) cores testing. To increase the utilization of the dictionary entries some methods are based on the correction of some bits before the loading of the entries into the scan chains. The coordinates of the bits that should be corrected are sent by the automatic test equipment (ATE), hence, the number of corrections should be relatively small. In this paper we propose a new method which is based on the use of an auxiliary dictionary of minor size for storing masks. To this end, we give an algorithm for the suitable selection of the masks so that any one of them is used for on the fly bit-flipping of parts of many dictionary entries, before they are loaded into the scan chains. The efficiency of the proposed method is supported with extensive experimental results.

Low capture power dictionary-based test data compression

Abstract: In this paper we first present a new test vector multi-bit correction technique for capture power reduction (average and peak) in scan based launch-on-capture transition delay testing of IP cores. Then we present a method which combines the test vector multi-bit correction technique and the dictionary based test data compression method of [11] in order to derive compressed test data with low capture power. Main characteristic of this technique is that the reduction of the capture power is obtained without (or with marginal) degradation of the compression efficiency. The efficiency of the proposed method is verified with simulations.

Preemptiv eBuilt-I nSelf-Tes tfo rIn-Fiel dStructura lTesting

Abstract: One-time factory testing of VLSI compo- nents after fabrication is insufficient in the deep submicron era. The products must be tested periodically in the field of application. Due to the complexity of the Systems on a Chip (SoCs), huge amounts of test data are required. How- ever in many embedded systems the capacity of the avail- able memory is a limited resource. Besides in real time embedded systems the in-field testing activities should be accommodated with the real-time constraints of the sys- tem. In this paper we at first show the suitability of the LFSR-based Test-Data Compression with Self-Stoppable Seeds method (10) for in-field testing and we give the re- quired enhancements so that can be used as a Preemptive Built-In Self-Test mechanism for in-field testing that is ap- plied at the idle time intervals of a hard real-time embedded system with sporadic tasks. Then, based on a probabilis- tic model and extensive simulations, we show that in the proposed method the time required to apply all the test vectors to the Circuit Under Test is many times smaller than the time required when the testing procedure consists from one or more non-preemptive test sessions. The pro- posed method achieves lower energy consumption for test- ing and significantly smaller fault detection latency times.

Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns

Abstract: This paper presents Star-EDT—a novel deterministic test compression scheme. The proposed solution seamlessly integrates with EDT-based compression and takes advantage of two key observations: 1) there exist clusters of test vectors that can detect many random-resistant faults with a cluster comprising a parent pattern and its derivatives obtained through simple transformations and 2) a significant majority of specified positions of ATPG-produced test cubes are typically clustered within a single or, at most, a few scan chains. The Star-EDT approach elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. Experimental results obtained for large industrial designs, including those with a new class of test points aware of ATPG-induced conflicts, illustrate feasibility of the proposed deterministic test scheme and are reported herein. In particular, they confirm that the Star-EDT can act as a valuable form of deterministic BIST.

Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression

Abstract: As technology processes scale up and design complexities grow, system-on-chip integration continues to rise rapidly According to these trends, increasing test data volume is one of the biggest challenges in the testing industry In this paper, we present a new test data compression method based on reusing a stored set with tri-state coding (TSC) For improving the compression efficiency, a twisted ring counter is used to reconfigure twist function It is useful to reuse previously used data for making next data by using the function of feedback of the ring counter Moreover, the TSC is used to increase the range information transmission without additional input ports Experimental results show that this compression method improves a compression ratio and a test time on both International Symposium on Circuits and Systems’89 and large International Test Conference’99 benchmark circuits in most cases compared to the results of the previous work without a heavy burden on the hardware

Thermal-Aware Test Data Compression Using Dictionary Based Coding

Abstract: In this paper, we have proposed a new thermal-aware test data compression technique using dictionary based coding. Huge test data volume and chip temperature are two major challenges for test engineers. Temperature of a chip can be reduced to a large extent by minimizing transition count in scan chains using efficient don't-care filling. On the other hand, high compression ratio can be achieved by filling the don't-cares intelligently to get more similar sub-vectors from test vectors. Although, both of the problems rely on don't-care bit filling, most of the existing works have considered them as separate problems. In our work, we have combined both temperature reduction and compression into a single problem and solved it. We present an intermediate approach that performs a trade-off between temperature and compression ratio. Experimental results on ISCAS'89 and ITC'99 benchmarks show the flexibility of the proposed method to achieve a balance between temperature and compression ratio.