Panayotis C. Andricacos

Bio: Panayotis C. Andricacos is an academic researcher from IBM. The author has contributed to research in topics: Electroplating & Copper. The author has an hindex of 26, co-authored 68 publications receiving 4787 citations. Previous affiliations of Panayotis C. Andricacos include GlobalFoundries.

Damascene Copper electroplating for chip interconnections

Abstract: Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 1990s, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system.

Damascene copper electroplating for chip interconnections

Abstract: Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

The chemistry of additives in damascene copper plating

Abstract: Copper plating baths used for forming integrated circuit interconnects typically contain three or four component additive mixtures which facilitate the superfilling of via holes and trench lines during damascene plating. Extensive study over the last two decades has provided researchers with an understanding of the underlying mechanisms. The role of cuprous intermediates in the copper deposition reaction has long been acknowledged, but it is not yet fully understood. In this paper we describe the results of an electrochemical study of the interaction of the organic additives used with copper and copper ions in solution. It is shown that cuprous intermediates near the copper surface affect the overpotential and the kinetics of plating. The additives regulate the presence of cuprous species on the surface; levelers and suppressors inhibit Cu+ formation, whereas accelerating additives enhance Cu+ formation. Acceleration by the bis(sodiumsulfopropyl) disulfide (SPS) additive results from accumulation of cuprous complexes near the surface. Adsorbed cuprous thiolate [Cu(I)(S(CH2)3 SO3H)ad] is formed through interaction of Cu+ ions and SPS rather than Cu2+ and mercaptopropane sulfonic acid (MPS).

Mechanisms for microstructure evolution in electroplated copper thin films near room temperature

Abstract: We present a model which accounts for the dramatic evolution in the microstructure of electroplated copper thin films near room temperature. Microstructure evolution occurs during a transient period of hours following deposition, and includes an increase in grain size, changes in preferred crystallographic texture, and decreases in resistivity, hardness, and compressive stress. The model is based on grain boundary energy in the fine-grained as-deposited films providing the underlying energy density which drives abnormal grain growth. As the grain size increases from the as-deposited value of 0.05–0.1 μm up to several microns, the model predicts a decreasing grain boundary contribution to electron scattering which allows the resistivity to decrease by tens of a percent to near-bulk values, as is observed. Concurrently, as the volume of the dilute grain boundary regions decreases, the stress is shown to change in the tensile direction by tens of a mega pascal, consistent with the measured values. The small ...

Vertical paddle plating cell

Abstract: An electroplating cell includes a floor, ceiling, front wall, and back wall forming a box having first and second opposite open ends. A rack for supporting an article to be electroplated is removably positioned vertically to close the first open end and includes a thief laterally surrounding the article to define a cathode. An anode is positioned vertically to close the second open end, with the assembly defining a substantially closed, six-sided inner chamber for receiving an electrolyte therein for electroplating the article. The article and surrounding thief are coextensively aligned with the anode, with the floor, ceiling, front and back walls being effective for guiding electrical current flux between the cathode and the anode. In a preferred embodiment, the cell is disposed as an inner cell inside an outer cell substantially filled with the electrolyte, and a paddle is disposed inside the inner cell for agitating the electrolyte therein. The rack is removable and installable vertically upwardly which allows for automated handling thereof.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Damascene copper electroplating for chip interconnections

Abstract: Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Phase change memory technology

Abstract: The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Structure Evolution During Processing of Polycrystalline Films

Abstract: ▪ Abstract Polycrystalline films have wide variety of applications in which their grain structures affect their performance and reliability. Thin film growth techniques and growth conditions affect grain shapes, the distribution of grain sizes, and the distribution of the crystallographic orientations of grains. Variations in these structural properties are affected by the conditions under which grain nucleation, growth, coarsening, coalescence, and thickening occur. General trends in structural evolution in polycystalline films, as a function of processing conditions and materials class, are discussed in terms of these fundamental kinetic processes.

Multifunctional 3D nanoarchitectures for energy storage and conversion.

Abstract: The design and fabrication of three-dimensional multifunctional architectures from the appropriate nanoscale building blocks, including the strategic use of void space and deliberate disorder as design components, permits a re-examination of devices that produce or store energy as discussed in this critical review. The appropriate electronic, ionic, and electrochemical requirements for such devices may now be assembled into nanoarchitectures on the bench-top through the synthesis of low density, ultraporous nanoarchitectures that meld high surface area for heterogeneous reactions with a continuous, porous network for rapid molecular flux. Such nanoarchitectures amplify the nature of electrified interfaces and challenge the standard ways in which electrochemically active materials are both understood and used for energy storage. An architectural viewpoint provides a powerful metaphor to guide chemists and materials scientists in the design of energy-storing nanoarchitectures that depart from the hegemony of periodicity and order with the promise—and demonstration—of even higher performance (265 references).