International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

In the past two decades, advances in programmable device technologies, in both the hardware and software arenas, have been extraordinary. The original application of rapid prototyping has been complemented with a large number of new applications that take advantage of the excellent characteristics of the latest devices. High speed, very large number of components, large number of supported protocols, and the addition of ready- to-use intellectual property cores make programmable devices the preferred choice of implementation and even deployment in mass production quantities. This paper surveys the advanced features, design tools, and application domains for field-programmable gate arrays (FPGAs). The main characteristics and structure of modern FPGAs are first described to show their versatility and abundance of available design resources. Software resources are also discussed, as they are the main enablers for the efficient exploitation of the design capabilities of these devices. Current application domains are described, such as configurable computing, dynamically reconfigurable systems, rapid system prototyping, communication processors and interfaces, and signal processing. This paper also presents the authors' prospective view of how FPGAs will evolve to enter new application domains in the future.

Features, Design Tools, and Application Domains of FPGAs

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Design, Automation, and Test in Europe

Radio Frequency Identification (RFID) is a technology which provides appealing opportunities to improve the management of information flow within the supply chain and security in the agri-food sector. Nowadays, food safety is considered a major requirement in several countries, in particular, the traceability of food products which is mandatory by law. Thus, technological implementation leading to traceability strengthening in the agri-food sector is crucial. The first aim of this review is to analyze the current developments in RFID technology in the agri-food sector, through an operative framework which organizes the literature and facilitate a quick content analysis identifying future research direction. RFID technology seems to be able to bring great opportunities to this sector; nevertheless, several constraints are slowing its adoption. This survey may provide readers with an exhaustive overview of opportunities and constraints for the wide adoption of RFID. The second aim of this review is to provide an updated analysis on the current developments of RFID technology for different product typologies within the agri-food industry, discussing at the same time its potential in technological and logistical development regarding different sectors of the production/distribution chain. As referenced here, RFID implementations in the agri-food sector are increasing at a fast rate, and technological advancement follows the applicability opportunities. However, real applications of RFID technologies are still limited because of various technical and economical obstacles which are also discussed.

A Review on Agri-food Supply Chain Traceability by Means of RFID Technology

This paper presents the radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions. Test experiments have been conducted to identify and to classify the single-event upsets (SEUs) in the configuration memory that induce single-event functional interrupt for the user-implemented circuit. Moreover the paper presents a new approach for assessing the effects of SEUs based on the combination of radiation testing and simulation-based fault injection tool. First experimental results show the FPGA look-up table (LUT) resources (used to implement combinatorial logic) are the most sensitive to SEUs, whereas interconnect resources are the most critical for the device cross section because they use the largest number of configuration bits. The analysis of experimental data underlines that the most probable error affecting interconnections is the shorting of two nets. This observation indicates that new fault models should be considered along with the classic stuck-at one model designing fault-tolerant architectures, which are intended for implementation in FPGA devices.

Errata to &#8220;Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs&#8221;

This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools dealing with the device configuration memory, we were able to make hypothesis on the meaning of every bit in the configuration memory. From the other side, radiation testing was exploited to validate the hypothesis and to gather experimental evidence about the correctness of the obtained results. As a major result, we can provide detailed information about the effects of SEUs affecting the configuration memory of a commercial FPGA device. As a second contribution, we describe a method for obtaining the same result with similar devices. Finally, the obtained results are crucial to allow the possible usage of SRAM-based FPGAs in safety-critical environments, e.g., by working on the place and route strategies of the supporting tools.

Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.

A new hybrid fault detection technique for systems-on-a-chip

Software-Based Self-Test is an effective methodology for devising the online testing of Systems-on-Chip. In the automotive field, a set of test programs to be run during mission mode is also called Core Self-Test library. This paper introduces many new contributions: (1) it illustrates the several issues that need to be taken into account when generating test programs for on-line execution; (2) it proposed an overall development flow based on ordered generation of test programs that is minimizing the computational efforts; (3) it is providing guidelines for allowing the coexistence of the Core Self-Test library with the mission application while guaranteeing execution robustness. The proposed methodology has been experimented on a large industrial case study. The coverage level reached after one year of team work is over 87 percent of stuck-at fault coverage, and execution time is compliant with the ISO26262 specification. Experimental results suggest that alternative approaches may request excessive evaluation time thus making the generation flow unfeasible for large designs.

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Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

Deep Learning, and in particular its implementation using Convolutional Neural Networks (CNNs), is currently one of the most intensively and widely used predictive models for safety-critical applications like autonomous driving assistance on pedestrian, objects and structures recognition. Today, ensuring the reliability of these innovations is becoming very important since they involve human lives. One of the peculiarities of the CNNs is the inherent resilience to errors due to the iterative nature of the learning process. In this work we present a method-ology to evaluate the impact of permanent faults affecting CNN exploited for automotive applications. Such a characterization is performed through a fault injection enviroment built upon on the darknet open source DNN framework. Results are shown about fault injection campaigns where permanent faults are affecting the connection weights in the LeNet and Yolo; the behavior of the corrupted CNN is classified according to the criticality of the introduced deviation.

Paolo Bernardi

Papers

Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”

Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

A new hybrid fault detection technique for systems-on-a-chip

Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

A Reliability Analysis of a Deep Neural Network

Paolo Bernardi

Papers

Errata to &#8220;Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs&#8221;

Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

A new hybrid fault detection technique for systems-on-a-chip

Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

A Reliability Analysis of a Deep Neural Network

Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”