scispace - formally typeset
Search or ask a question
Author

Paolo Pavan

Other affiliations: University of Padua, Numonyx, SEMATECH  ...read more
Bio: Paolo Pavan is an academic researcher from University of Modena and Reggio Emilia. The author has contributed to research in topics: Bipolar junction transistor & Resistive random-access memory. The author has an hindex of 30, co-authored 220 publications receiving 5151 citations. Previous affiliations of Paolo Pavan include University of Padua & Numonyx.


Papers
More filters
Journal ArticleDOI
TL;DR: In this paper, a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation is presented, which is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction.
Abstract: This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250/spl deg/C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 /spl mu/m process, the area of a bit is 0.315 /spl mu/m/sup 2/ and 0.188 /spl mu/m/sup 2/ in 0.25 /spl mu/m technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications.

1,170 citations

Journal ArticleDOI
01 Aug 1997
TL;DR: Basic operations and charge-injection mechanisms that are most commonly used in actual flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature.
Abstract: The aim of this paper is to give a thorough overview of flash memory cells. Basic operations and charge-injection mechanisms that are most commonly used in actual flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature. New cell structures and architectural solutions have been surveyed to highlight the evolution of the flash memory technology, oriented to both reducing cell size and upgrading product functions. The subject is of extreme interest: new concepts involving new materials, structures, principles, or applications are being continuously introduced. The worldwide semiconductor memory market seems ready to accept many new applications in fields that are not specific to traditional nonvolatile memories.

736 citations

Journal ArticleDOI
TL;DR: This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained.
Abstract: Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, with electronic nonvolatile memories being those that have received the most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

441 citations

Journal ArticleDOI
TL;DR: In this paper, the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS) is analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN.
Abstract: In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance.

96 citations


Cited by
More filters
Journal ArticleDOI
TL;DR: In this article, the authors proposed a method of modeling and simulation of photovoltaic arrays by adjusting the curve at three points: open circuit, maximum power, and short circuit.
Abstract: This paper proposes a method of modeling and simulation of photovoltaic arrays. The main objective is to find the parameters of the nonlinear I-V equation by adjusting the curve at three points: open circuit, maximum power, and short circuit. Given these three points, which are provided by all commercial array data sheets, the method finds the best I-V equation for the single-diode photovoltaic (PV) model including the effect of the series and parallel resistances, and warranties that the maximum power of the model matches with the maximum power of the real array. With the parameters of the adjusted I-V equation, one can build a PV circuit model with any circuit simulator by using basic math blocks. The modeling method and the proposed circuit model are useful for power electronics designers who need a simple, fast, accurate, and easy-to-use modeling method for using in simulations of PV systems. In the first pages, the reader will find a tutorial on PV devices and will understand the parameters that compose the single-diode PV model. The modeling method is then introduced and presented in details. The model is validated with experimental data of commercial PV arrays.

3,811 citations

Book
Yuan Taur1, Tak H. Ning1
01 Jan 2016
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

2,680 citations

Journal ArticleDOI
TL;DR: This paper presents an overview of the RF-EHNs including system architecture, RF energy harvesting techniques, and existing applications, and explores various key design issues according to the network types, i.e., single-hop networks, multiantenna networks, relay networks, and cognitive radio networks.
Abstract: Radio frequency (RF) energy transfer and harvesting techniques have recently become alternative methods to power the next-generation wireless networks As this emerging technology enables proactive energy replenishment of wireless devices, it is advantageous in supporting applications with quality-of-service requirements In this paper, we present a comprehensive literature review on the research progresses in wireless networks with RF energy harvesting capability, which is referred to as RF energy harvesting networks (RF-EHNs) First, we present an overview of the RF-EHNs including system architecture, RF energy harvesting techniques, and existing applications Then, we present the background in circuit design as well as the state-of-the-art circuitry implementations and review the communication protocols specially designed for RF-EHNs We also explore various key design issues in the development of RF-EHNs according to the network types, ie, single-hop networks, multiantenna networks, relay networks, and cognitive radio networks Finally, we envision some open research directions

2,352 citations

Journal ArticleDOI
TL;DR: In this paper, a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation is presented, which is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction.
Abstract: This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250/spl deg/C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 /spl mu/m process, the area of a bit is 0.315 /spl mu/m/sup 2/ and 0.188 /spl mu/m/sup 2/ in 0.25 /spl mu/m technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications.

1,170 citations

Book
29 Sep 2011
TL;DR: The Fifth Edition of Computer Architecture focuses on this dramatic shift in the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices.
Abstract: The computing world today is in the middle of a revolution: mobile clients and cloud computing have emerged as the dominant paradigms driving programming and hardware innovation today. The Fifth Edition of Computer Architecture focuses on this dramatic shift, exploring the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices. Each chapter includes two real-world examples, one mobile and one datacenter, to illustrate this revolutionary change. Updated to cover the mobile computing revolutionEmphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next")Includes three review appendices in the printed text. Additional reference appendices are available online.Includes updated Case Studies and completely new exercises.

984 citations