scispace - formally typeset
Search or ask a question
Author

Patrick S. Goley

Other affiliations: Virginia Tech
Bio: Patrick S. Goley is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Molecular beam epitaxy & Heterojunction. The author has an hindex of 8, co-authored 26 publications receiving 273 citations. Previous affiliations of Patrick S. Goley include Virginia Tech.

Papers
More filters
Journal ArticleDOI
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.

128 citations

Journal ArticleDOI
Michael Clavel1, Patrick S. Goley1, Nikhil Jain1, Yan Zhu1, Mantu K. Hudait1 
TL;DR: The structural, morphological, and energy band alignment properties of biaxial tensile-strained germanium epilayers, grown in-situ on GaAs via a linearly graded InxGa1−xAs buffer architecture and utilizing dual chamber molecular beam epitaxy, were investigated in this article.
Abstract: The structural, morphological, and energy band alignment properties of biaxial tensile-strained germanium epilayers, grown in-situ on GaAs via a linearly graded InxGa1−xAs buffer architecture and utilizing dual chamber molecular beam epitaxy, were investigated. Precise control over the growth conditions yielded a tunable in-plane biaxial tensile strain within the Ge thin films that was modulated by the underlying InxGa1−xAs “virtual substrate” composition. In-plane tensile strains up to 1.94% were achieved without Ge relaxation for layer thicknesses of 15 to 30 nm. High-resolution x-ray diffraction supported the pseudomorphic nature of the Ge/InxGa1−xAs interface, indicating a quasi-ideal stress transfer to the Ge lattice. High-resolution transmission electron microscopy revealed defect-free Ge epitaxy and a sharp, coherent interface at the Ge/InxGa1−xAs heterojunction. Surface morphology characterization using atomic force microscopy exhibited symmetric, 2-D cross-hatch patterns with root mean square roughness less than 4.5 nm. X-ray photoelectron spectroscopic analysis revealed a positive, monotonic trend in band offsets for increasing tensile strain. The superior structural and band alignment properties of strain-engineered epitaxial Ge suggest that tensile-strained Ge/InxGa1−xAs heterostructures show great potential for future high-performance tunnel field-effect transistor architectures requiring flexible device design criteria while maintaining low power, energy-efficient device operation.

33 citations

Journal ArticleDOI
Mantu K. Hudait1, Michael Clavel1, Patrick S. Goley1, Nikhil Jain1, Yan Zhu1 
TL;DR: The heterogeneous integration of device-quality epitaxial Ge on Si using composite AlAs/GaAs large bandgap buffer, grown by molecular beam epitaxy that is suitable for fabricating low-power fin field-effect transistors required for continuing transistor miniaturization is reported on.
Abstract: Germanium-based materials and device architectures have recently appeared as exciting material systems for future low-power nanoscale transistors and photonic devices. Heterogeneous integration of germanium (Ge)-based materials on silicon (Si) using large bandgap buffer architectures could enable the monolithic integration of electronics and photonics. In this paper, we report on the heterogeneous integration of device-quality epitaxial Ge on Si using composite AlAs/GaAs large bandgap buffer, grown by molecular beam epitaxy that is suitable for fabricating low-power fin field-effect transistors required for continuing transistor miniaturization. The superior structural quality of the integrated Ge on Si using AlAs/GaAs was demonstrated using high-resolution x-ray diffraction analysis. High-resolution transmission electron microscopy confirmed relaxed Ge with high crystalline quality and a sharp Ge/AlAs heterointerface. X-ray photoelectron spectroscopy demonstrated a large valence band offset at the Ge/AlAs interface, as compared to Ge/GaAs heterostructure, which is a prerequisite for superior carrier confinement. The temperature-dependent electrical transport properties of the n-type Ge layer demonstrated a Hall mobility of 370 cm2/Vs at 290 K and 457 cm2/Vs at 90 K, which suggests epitaxial Ge grown on Si using an AlAs/GaAs buffer architecture would be a promising candidate for next-generation high-performance and energy-efficient fin field-effect transistor applications.

31 citations

Journal ArticleDOI
TL;DR: STO, when used as an interlayer between metal and n-type (4 × 10(18) cm(-3)) epitaxial Ge in metal-insulator-semiconductor (MIS) structures, showed a 1000 times increase in current density as well as a decrease in specific contact resistance.
Abstract: SrTiO3 integration on crystallographic oriented (100), (110), and (111) epitaxial germanium (Ge) exhibits a potential for a new class of nanoscale transistors. Germanium is attractive due to its superior transport properties while SrTiO3 (STO) is promising due to its high relative permittivity, both being critical parameters for next-generation low-voltage and low-leakage metal-oxide semiconductor field-effect transistors. The sharp heterointerface between STO and each crystallographically oriented Ge layer, studied by cross-sectional transmission electron microscopy, as well as band offset parameters at each heterojunction offers a significant advancement for designing a new generation of ferroelectric-germanium based multifunctional devices. Moreover, STO, when used as an interlayer between metal and n-type (4 × 1018 cm–3) epitaxial Ge in metal–insulator–semiconductor (MIS) structures, showed a 1000 times increase in current density as well as a decrease in specific contact resistance. Furthermore, the ...

24 citations

Journal ArticleDOI
TL;DR: The successful heterogeneous integration of tunable tensile-strained germanium epilayers heterogeneously integrated on silicon (Si) paves the way for the design and implementation of novel Ge-based photonic devices on the Si technology platform.
Abstract: The growth, structural and optical properties, and energy band alignments of tensile-strained germanium (e-Ge) epilayers heterogeneously integrated on silicon (Si) were demonstrated for the first time. The tunable e-Ge thin films were achieved using a composite linearly graded InxGa1–xAs/GaAs buffer architecture grown via solid source molecular beam epitaxy. High-resolution X-ray diffraction and micro-Raman spectroscopic analysis confirmed a pseudomorphic e-Ge epitaxy whereby the degree of strain varied as a function of the InxGa1–xAs buffer indium alloy composition. Sharp heterointerfaces between each e-Ge epilayer and the respective InxGa1–xAs strain template were confirmed by detailed strain analysis using cross-sectional transmission electron microscopy. Low-temperature microphotoluminescence measurements confirmed both direct and indirect bandgap radiative recombination between the Γ and L valleys of Ge to the light-hole valence band, with L-lh bandgaps of 0.68 and 0.65 eV demonstrated for the 0.82 ±...

23 citations


Cited by
More filters
Journal ArticleDOI
TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

512 citations

Journal ArticleDOI
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.

116 citations

Journal ArticleDOI
TL;DR: A low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2 p-FET, with a solution-processed WSe 2 Resistive Random Access Memory is demonstrated.
Abstract: 3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2 p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2 p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems. Designing efficient, scalable and low-thermal-budget 2D Materials for 3D integration remains a challenge. Here, the authors report the development of a hybrid-(solution-processed-exfoliated) integration of 2D Material based 1T1R which uses a multilayer WSe2 p-FET and a multilayer printed WSe2 RRAM.

90 citations

Journal ArticleDOI
TL;DR: It is shown that the Coulomb interaction-induced self-energy corrections in real space are sufficiently nonlocal to be manipulated externally, but still local enough to induce spatially sharp interfaces within a single homogeneous monolayer to form heterojunctions.
Abstract: We propose to create lateral heterojunctions in two-dimensional materials based on nonlocal manipulations of the Coulomb interaction using structured dielectric environments. By means of ab initio calculations for MoS2 as well as generic semiconductor models, we show that the Coulomb interaction-induced self-energy corrections in real space are sufficiently nonlocal to be manipulated externally, but still local enough to induce spatially sharp interfaces within a single homogeneous monolayer to form heterojunctions. We find a type-II heterojunction band scheme promoted by a laterally structured dielectric environment, which exhibits a sharp band gap crossover within less than 5 unit cells.

85 citations

Journal ArticleDOI
TL;DR: A high-yield and high-throughput method is used to demonstrate nanometer-thin photodetectors with significantly enhanced light absorption based on nanocavity interference mechanism, which exhibit unique optoelectronic properties, such as the strong field effect and spectral selectivity.
Abstract: Miniaturization of optoelectronic devices offers tremendous performance gain. As the volume of photoactive material decreases, optoelectronic performance improves, including the operation speed, the signal-to-noise ratio, and the internal quantum efficiency. Over the past decades, researchers have managed to reduce the volume of photoactive materials in solar cells and photodetectors by orders of magnitude. However, two issues arise when one continues to thin down the photoactive layers to the nanometer scale (for example, <50 nm). First, light-matter interaction becomes weak, resulting in incomplete photon absorption and low quantum efficiency. Second, it is difficult to obtain ultrathin materials with single-crystalline quality. We introduce a method to overcome these two challenges simultaneously. It uses conventional bulk semiconductor wafers, such as Si, Ge, and GaAs, to realize single-crystalline films on foreign substrates that are designed for enhanced light-matter interaction. We use a high-yield and high-throughput method to demonstrate nanometer-thin photodetectors with significantly enhanced light absorption based on nanocavity interference mechanism. These single-crystalline nanomembrane photodetectors also exhibit unique optoelectronic properties, such as the strong field effect and spectral selectivity.

74 citations