Patrick S. Goley

Bio: Patrick S. Goley is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Molecular beam epitaxy & Heterojunction. The author has an hindex of 8, co-authored 26 publications receiving 273 citations. Previous affiliations of Patrick S. Goley include Virginia Tech.

A Co-Integrated Silicon-Based Electronic-Photonic Wideband, High-Power Signal Source

Abstract: A novel co-integrated electronic-photonic distributed photo-mixer-amplifier is presented that improves the bandwidth and gain of the system. An RF signal with an output power of 10 dBm across the bandwidth of 50 GHz was achieved.

Modeling Transient Loss Due to Ionizing Particles in Silicon Photonic Waveguides

Abstract: A general, computationally efficient, physics-based model for the continuous time-domain description of transient loss in silicon (Si) photonic waveguides due to impinging ionizing particles is presented. The model combines Beer–Lambert and Drude formalisms with the ambipolar transport equation (ATE) and applies a number of carefully vetted simplifying assumptions to obtain a highly compact form. The model is validated using nanosecond pulses of tightly focused 639-nm laser light to induce localized high-level generation events and mimic heavy-ion strikes within Si photonic waveguides of varying geometry. Electron–hole pairs (ehps) generated in these events cause free-carrier absorption (FCA) of a continuous 1535-nm probe signal in the waveguide, which is observed as a transient drop in detected photocurrent on a high-speed oscilloscope. Measured transients show excellent agreement with model predictions.

Localized Excitation of Silicon Photonic Waveguides for Measurement of Free-Carrier Lifetime and Surface Recombination Velocity

Abstract: A pulsed 639 nm laser is focused to strongly excite 1-µm scale lengths of silicon photonic waveguide. Extraction of the local free-carrier lifetime and recombination velocity information from time-resolved transmission of a continuous 1535 nm probe laser is presented.

Towards a monolithic, substrate-reusable and an all-epitaxial design for III–V-on-Si solar cells

Abstract: Integration of III–V multijunction solar cells on Si substrate can address the future levelized cost of energy by unifying the high-efficiency merits of III–V materials with the low-cost and abundance of Si. A Si-compatible monolithically integrated 3J InGaP/GaAs/Ge-Si cell design with a hybrid Ge-Si bottom cell is investigated. Utilizing a combination of comprehensive modeling and experimental material characterization techniques, we present our results for ultrathin epitaxial Ge directly grown on Si substrate using molecular beam epitaxy. Virtual “Ge-on-Si” substrates could provide a large-area, low-cost alternative to expensive GaAs wafers, a promising step towards realizing monolithic, high-efficiency and low-cost III–V-on-Si photovoltaics.

Plastic Relaxation of Highly Tensile Strained (100) Ge/InGaAs Heterostructures

Abstract: Biaxial tensile strain has been shown to greatly enhance the optoelectronic properties of epitaxial germanium (Ge) layers. As a result, tensile-Ge (et-Ge) layers grown on larger lattice constant InGaAs or GeSn have attracted great research interest. However, no previous studies have investigated the plastic relaxation occurring in these et-Ge layers. Here, we experimentally demonstrate that plastic relaxation occurs in nearly all et-Ge epitaxial layers that are of practical interest for optoelectronic applications, even when layers may still exhibit strain-enhanced characteristics. We show arrays of misfit dislocations (MDs), which are mostly disassociated, form at the et-Ge/InGaAs interface for et-Ge layers as thin as 15 nm with less than 1% total mismatch. Wedge geometry of plain view transmission electron microscopy (PV-TEM) foils is utilized to carry out a depth dependent investigation MD spacing for a range of et-Ge/InGaAs heterostructures. MD spacing measured by PV-TEM is correlated to et-Ge layer relaxation measured by highresolution x-ray diffraction. We confirm very low relaxation (< 10% relaxed) in et-Ge layers does not imply they have been coherently grown. We demonstrate plastic relaxation in the et-Ge layer is acutely sensitive to grown-in threading dislocations (TDs) in the template material, and that reducing TD density is critical for maximizing strain retention. Given that et-Ge layer thicknesses of 150+ nm with greater than 1% tensile strain are desired for optoelectronic devices, this work suggests that MDs may inevitably be present at et-Ge/InGaAs heterointerfaces in practical devices, and that the effect of MDs on optoelectronic performance must be better understood.

High-K materials and metal gates for CMOS applications

Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

Synthesis and Characterization of Hexagonal Boron Nitride as a Gate Dielectric

Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.

All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration.

Abstract: 3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2 p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2 p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems. Designing efficient, scalable and low-thermal-budget 2D Materials for 3D integration remains a challenge. Here, the authors report the development of a hybrid-(solution-processed-exfoliated) integration of 2D Material based 1T1R which uses a multilayer WSe2 p-FET and a multilayer printed WSe2 RRAM.

Two-Dimensional Heterojunctions from Nonlocal Manipulations of the Interactions

Abstract: We propose to create lateral heterojunctions in two-dimensional materials based on nonlocal manipulations of the Coulomb interaction using structured dielectric environments. By means of ab initio calculations for MoS2 as well as generic semiconductor models, we show that the Coulomb interaction-induced self-energy corrections in real space are sufficiently nonlocal to be manipulated externally, but still local enough to induce spatially sharp interfaces within a single homogeneous monolayer to form heterojunctions. We find a type-II heterojunction band scheme promoted by a laterally structured dielectric environment, which exhibits a sharp band gap crossover within less than 5 unit cells.

Single-crystalline germanium nanomembrane photodetectors on foreign nanocavities.

Abstract: Miniaturization of optoelectronic devices offers tremendous performance gain. As the volume of photoactive material decreases, optoelectronic performance improves, including the operation speed, the signal-to-noise ratio, and the internal quantum efficiency. Over the past decades, researchers have managed to reduce the volume of photoactive materials in solar cells and photodetectors by orders of magnitude. However, two issues arise when one continues to thin down the photoactive layers to the nanometer scale (for example, <50 nm). First, light-matter interaction becomes weak, resulting in incomplete photon absorption and low quantum efficiency. Second, it is difficult to obtain ultrathin materials with single-crystalline quality. We introduce a method to overcome these two challenges simultaneously. It uses conventional bulk semiconductor wafers, such as Si, Ge, and GaAs, to realize single-crystalline films on foreign substrates that are designed for enhanced light-matter interaction. We use a high-yield and high-throughput method to demonstrate nanometer-thin photodetectors with significantly enhanced light absorption based on nanocavity interference mechanism. These single-crystalline nanomembrane photodetectors also exhibit unique optoelectronic properties, such as the strong field effect and spectral selectivity.