In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

A comprehensive survey of thinning methodologies is presented. A wide range of thinning algorithms, including iterative deletion of pixels and nonpixel-based methods, is covered. Skeletonization algorithms based on medial axis and other distance transforms are not considered. An overview of the iterative thinning process and the pixel-deletion criteria needed to preserve the connectivity of the image pattern is given first. Thinning algorithms are then considered in terms of these criteria and their modes of operation. Nonpixel-based methods that usually produce a center line of the pattern directly in one pass without examining all the individual pixels are discussed. The algorithms are considered in great detail and scope, and the relationships among them are explored. >

Thinning methodologies-a comprehensive survey

A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.

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A reliable approach to charge-pumping measurements in MOS transistors

A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g/sub m//I/sub D/ and the normalized current I/sub D//(W/L). The g/sub m//I/sub D/ indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).

A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

The gm/ID sizing methodology. Sizing the Intrinsic Gain Stage by means of experimental data or a model like the E.K.V./A.C.M. model. Sizing short channel devices with parameters that are functions of bias conditions. Parameter acquisition, accuracy, examples. Application to the sizing of low-power low-voltage CMOS circuits like the Miller Op. Amp, Barranco's current sources, etc.

Sizing CMOS circuits by means of the gm/ID methodology and a compact model

A correlator module using the Pseudo Random Comparison (PRC) algorithm has been designed and fabricated in a standard 8 ?m PMOS process. It demonstrated the validity of the principle and the feasibility of a low cost integrated correlator or RMS meter based on that principle. The chip runs at frequenties up to 2 MHz, dissipates 90 mW and its size is 2.4mm2

An Integrated Binary Correlator Module

Systematic Design of Analog CMOS Circuits with Lookup Tables

Basic Sizing Using the g m / I D Methodology

An interesting representation of the drain current can be obtained when the expression below is used for the drain current (Tsividis 1999): 

$${I}_{D} = \mu {C}_{ox}^{{\prime}}\frac{W} {L} \cdot {\int \nolimits }_{{V }_{S}}^{{V }_{D} }\left (- \frac{{Q}_{i}^{{\prime}}} {{C}_{ox}^{{\prime}}}\right )\,\mathit{dV }\,$$

(3.1)

The equation is derived from, the proportionality of the minority carrier density to the exponential function acknowledged by Boltzmann statistics: 

$${Q}_{i}^{{\prime}}\propto \exp \left (\frac{{\psi }_{S} - 2{\phi }_{B} - V } {{U}_{T}} \right )$$

(3.2)

Paul Jespers

Papers

Sizing CMOS circuits by means of the gm/ID methodology and a compact model

An Integrated Binary Correlator Module

Systematic Design of Analog CMOS Circuits with Lookup Tables

Basic Sizing Using the g m / I D Methodology

Graphical Interpretation of the Charge Sheet Model