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Paul S. Zuchowski

Bio: Paul S. Zuchowski is an academic researcher from IBM. The author has contributed to research in topics: Integrated circuit & Integrated circuit design. The author has an hindex of 17, co-authored 46 publications receiving 1420 citations.

Papers
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Proceedings ArticleDOI
10 Nov 2002
TL;DR: In this article, the authors discuss Voltage Islands, a system architecture and chip implementation methodology that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs.
Abstract: This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption. Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.

331 citations

Proceedings ArticleDOI
10 Nov 2002
TL;DR: A new hybrid ASIC/FPGA chip architecture that is being developed in collaboration between IBM and Xilinx is introduced, and some of the design challenges this offers for designers and CAD developers are highlighted.
Abstract: This paper introduces a new hybrid ASIC/FPGA chip architecture that is being developed in collaboration between IBM and Xilinx, and highlights some of the design challenges this offers for designers and CAD developers. We review recent data from both the ASIC and FPGA industries, including technology features, and trends in usage and costs. This background data indicates that there are advantages to using standard ASICs and FPGAs for many applications, but technical and financial considerations are increasingly driving the need for a hybrid ASIC/FPGA architecture at specific volume tiers and technology nodes. As we describe the hybrid chip architecture ,we point out evolving tool and methodology issues that will need to be addressed to enable customers to effectively design hybrid ASIC/FPGAs. The discussion highlights specific automation issues in the areas of logic partitioning, logic simulation, verification, timing, layout and test.

328 citations

Proceedings ArticleDOI
07 Nov 2004
TL;DR: In this paper, the authors introduce the concepts of systematic interdie variation, systematic intra-die variation and intra die random variation and show that by treating these forms of variations differently, they can achieve design closure with less guard-banding than traditional methods.
Abstract: With each semiconductor process node, the impacts on performance of environmental and semiconductor process variations become a larger portion of the cycle time of the product. Simple guard-banding for these effects leads to increased product development times and uncompetitive products. In addition, traditional static timing methodologies are unable to cope with the large number of permutations of process, voltage, and temperature corners created by these independent sources of variation. In this paper we will discuss the sources of variation; by introducing the concepts of systematic inter-die variation, systematic intra-die variation and intra-die random variation. We will show that by treating these forms of variations differently, we can achieve design closure with less guard-banding than traditional methods.

111 citations

Patent
15 Jun 2004
TL;DR: In this article, a method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands.
Abstract: A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.

70 citations

Patent
10 Mar 1998
TL;DR: In this article, the capacitance and resistance of each global wire on the chip, one wire at a time, are calculated by searching neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire.
Abstract: A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances. The invention can also provide for wires and spaces of various types and widths not provided for in the tables and for calculation of net to net coupling capacitances.

64 citations


Cited by
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Journal ArticleDOI
TL;DR: Experimental measurements of the differences between a 90- nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic are presented.
Abstract: This paper presents experimental measurements of the differences between a 90-nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic. We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to FPGA makers on the deficiencies to attack and, thereby, improve FPGAs. We describe the methodology by which the measurements were obtained and show that, for circuits containing only look-up table-based logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 35. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories. We find that these blocks reduce this average area gap significantly to as little as 18 for our benchmarks, and we estimate that extensive use of these hard blocks could potentially lower the gap to below five. The ratio of critical-path delay, from FPGA to ASIC, is roughly three to four with less influence from block memory and hard multipliers. The dynamic power consumption ratio is approximately 14 times and, with hard blocks, this gap generally becomes smaller

1,078 citations

Proceedings ArticleDOI
22 Feb 2006
TL;DR: Experimental measurements of the differences between a 90- nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic are presented.
Abstract: This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed hoices between these two media and to give insight to FPGA makers on the deficiencies to attack and thereby improve FPGAs. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power onsumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller.

635 citations

Book
18 Apr 2008
TL;DR: This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures.
Abstract: Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

491 citations

Proceedings ArticleDOI
10 Nov 2002
TL;DR: A new hybrid ASIC/FPGA chip architecture that is being developed in collaboration between IBM and Xilinx is introduced, and some of the design challenges this offers for designers and CAD developers are highlighted.
Abstract: This paper introduces a new hybrid ASIC/FPGA chip architecture that is being developed in collaboration between IBM and Xilinx, and highlights some of the design challenges this offers for designers and CAD developers. We review recent data from both the ASIC and FPGA industries, including technology features, and trends in usage and costs. This background data indicates that there are advantages to using standard ASICs and FPGAs for many applications, but technical and financial considerations are increasingly driving the need for a hybrid ASIC/FPGA architecture at specific volume tiers and technology nodes. As we describe the hybrid chip architecture ,we point out evolving tool and methodology issues that will need to be addressed to enable customers to effectively design hybrid ASIC/FPGAs. The discussion highlights specific automation issues in the areas of logic partitioning, logic simulation, verification, timing, layout and test.

328 citations

Proceedings ArticleDOI
01 Nov 1998
TL;DR: A comprehensive approach to accurately characterize the device and interconnect characteristics of present and future process generations is described, resulting in the generation of a representative strawman technology that is used in conjunction with analytical model simulation tools and empirical design data to obtain a realistic picture of the future of circuit design.
Abstract: We take a fresh look at the problems posed by deep submicron (DSM) geometries and re-open the investigation into how DSM effects are most likely to affect future design methodologies. We describe a comprehensive approach to accurately characterize the device and interconnect characteristics of present and future process generations. This approach results in the generation of a representative strawman technology that is used in conjunction with analytical model simulation tools and empirical design data to obtain a realistic picture of the future of circuit design. We then proceed to quantify the precise impact of interconnect, including delay degradation due to noise, on high performance ASIC designs. Having determined the role of interconnect in performance, we then reconsider the impact of future processes on ASIC design methodology.

322 citations