Paul W. Mertens

Bio: Paul W. Mertens is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Gate oxide & Silicon. The author has an hindex of 20, co-authored 67 publications receiving 1217 citations.

Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance

Abstract: 7cm 2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at 6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for p/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H2 anneal for device performance is shown.

Non-Gaussian behavior and anticorrelations in ultrathin gate oxides after soft breakdown

Abstract: The time dependence of the gate voltage VG(t) after soft breakdown of metal-oxide-semiconductor capacitors with a 2.4 nm SiO2 layer has been measured. It is found that the VG(t) fluctuation distributions are non-Gaussian, but can be described by a Levy stable distribution. The long-range correlations in VG(t) are investigated within the detrended fluctuation analysis. The Hurst exponent is found to be H=0.25±0.04 independent of the value of the stress current density J. It is argued that these are universal features of soft breakdown and are due to trapping–detrapping of electrons in and away from the primary percolation path.

Impact of organic contamination on thin gate oxide quality

Abstract: The impact of organic contamination on the quality of 5-nm-thick gate oxide structures, both before and after gate oxidation, is studied. Sources of organic contamination are chemical surface modification (i.e. hexamethyldisilazane priming), wafer box storage and extended vacuum exposure. Gate oxide integrity is evaluated electrically. The origin and/or nature of the organic contamination is seen to have different effects on the electrical breakdown. Care should be taken when exposing silicon wafers to organic contamination prior to processing. Especially when contamination occurs at the SiO2/polysilicon interface, i.e. prior to a non-oxidizing process step, organics can be extremely deleterious.

Fundamental study of the removal mechanisms of nano-sized particles using brush scrubber cleaning

Abstract: To ensure high device yields, wafer surface contamination and defects must be monitored and controlled during the entire process of semiconductor manufacturing. Particle surface concentrations on the wafers, mostly related to chemical mechanical polishing (CMP) processes, must be kept at the lowest possible levels. Brush scrubber cleaning has the potential to achieve this goal. However, the particle removal mechanisms are still under discussion especially the removal of nano-sized particles. This paper investigates the interactions between the particle, the brush and the wafer surface and explores the potential and limitations of the brush scrubbing technique. Furthermore the effect of the various brush/wafer parameters on the particle removal efficiency (PRE) is studied. From a mechanistic viewpoint it is shown that brush scrubbing acts in a mixed lubrication regime. From an extensive analysis of the relevant forces and moments it can be concluded that in the hydrodynamic lubrication regime, particles ar...

Cost-effective cleaning and high-quality thin gate oxides

Abstract: Some recent findings in the area of wafer cleaning and thin oxide properties are presented in this paper. Results are shown for a practical implementation of a simplified cleaning concept that combines excellent performance in terms of metal and particle removal with low chemical and DI-water consumption. The effect of organic contamination on ultrathin gate-oxide integrity is illustrated, and the feasibility of using ozonated DI water as an organic removal step is discussed. Metal outplating from HF and HF/HCI solutions is investigated. Also, the final rinsing step is critically evaluated. It is demonstrated that Si surface roughness without the presence of metal contaminants does not degrade gate-oxide integrity. Finally, some critical remarks on the reliability measurements for ultrathin gate oxides are given; it is shown that erroneous conclusions can be drawn from constant-current charge-to-breakdown measurements.

Multifractal Detrended Fluctuation Analysis of Nonstationary Time Series

Abstract: We develop a method for the multifractal characterization of nonstationary time series, which is based on a generalization of the detrended fluctuation analysis (DFA). We relate our multifractal DFA method to the standard partition function-based multifractal formalism, and prove that both approaches are equivalent for stationary signals with compact support. By analyzing several examples we show that the new method can reliably determine the multifractal scaling behavior of time series. By comparing the multifractal DFA results for original series with those for shuffled series we can distinguish multifractality due to long-range correlations from multifractality due to a broad probability density function. We also compare our results with the wavelet transform modulus maxima method, and show that the results are equivalent.

Detecting long-range correlations with detrended fluctuation analysis

Abstract: We examine the detrended fluctuation analysis (DFA), which is a well-established method for the detection of long-range correlations in time series. We show that deviations from scaling which appear at small time scales become stronger in higher orders of DFA, and suggest a modified DFA method to remove them. The improvement is necessary especially for short records that are affected by non-stationarities. Furthermore, we describe how crossovers in the correlation behavior can be detected reliably and determined quantitatively and show how several types of trends in the data affect the different orders of DFA.

Alternative dielectrics to silicon dioxide for memory and logic devices

Abstract: The silicon-based microelectronics industry is rapidly approaching a point where device fabrication can no longer be simply scaled to progressively smaller sizes. Technological decisions must now be made that will substantially alter the directions along which silicon devices continue to develop. One such challenge is the need for higher permittivity dielectrics to replace silicon dioxide, the properties of which have hitherto been instrumental to the industry's success. Considerable efforts have already been made to develop replacement dielectrics for dynamic random-access memories. These developments serve to illustrate the magnitude of the now urgent problem of identifying alternatives to silicon dioxide for the gate dielectric in logic devices, such as the ubiquitous field-effect transistor.

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Abstract: The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Fabrication of Single-Crystalline Silicon Nanowires by Scratching a Silicon Surface with Catalytic Metal Particles†

Abstract: A novel strategy for preparing large-area, oriented silicon nanowire (SiNW) arrays on silicon substrates at near room temperature by localized chemical etching is presented. The strategy is based on metal-induced (either by Ag or Au) excessive local oxidation and dissolution of a silicon substrate in an aqueous fluoride solution. The density and size of the as-prepared SiNWs depend on the distribution of the patterned metal particles on the silicon surface. High-density metal particles facilitate the formation of silicon nanowires. Well-separated, straight nanoholes are dug along the Si block when metal particles are well dispersed with a large space between them. The etching technique is weakly dependent on the orientation and doping type of the silicon wafer. Therefore, SiNWs with desired axial crystallographic orientations and doping characteristics are readily obtained. Detailed scanning electron microscopy observations reveal the formation process of the silicon nanowires, and a reasonable mechanism is proposed on the basis of the electrochemistry of silicon and the experimental results.