There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

/pdf/low-voltage-tunnel-transistors-for-beyond-cmos-logic-3w5c8knrc5.pdf

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

https://www.silvaco.co.kr/tech_lib_TCAD/simulationstandard/2008/jan_feb_mar/a2/jan-feb-mar08_a2.pdf

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.

Complementary tunneling transistor for low power application

In this brief, a novel U-shape-channel tunneling field-effect transistor (UTFET) with a SiGe source region is investigated by 2-D technology computer aided design simulation. The enlarged tunneling area and enhanced tunneling rate dramatically increase the tunneling current when the device is turned on. Meanwhile, the off-leakage current of UTFET is suppressed because of the extended physical channel length. The on-state tunneling current of UTFET can be further improved by introducing an n+-doped Si delta layer under the source region. The inserted delta layer significantly shortens the band-to-band tunneling path, enlarges tunneling area, and thus enhances the tunneling rate of this device. The average value of the subthreshold swing (SS) of the optimized UTFET is 58 mV/dec when VGS is varied from 0 to 0.46 V. Using the SiGe-source UTFET structure with a delta layer, the merits of low leakage current, high drive current, and ultralow SS can be realized simultaneously.

Design of U-Shape Channel Tunnel FETs With SiGe Source Regions

This work presents tunneling field effect transistors (TFET) fabricated with 130nm and 90nm process flows. Good performance of the TFET is achieved. A novel mixed TFET/CMOS (TCMOS) logic family exhibits the advantages with respect to power consumption. For the first time experimental results are presented for a TCMOS ring-oscillator based on a p-channel MOSFET and n-channel TFET. The benefits of the TFET used in analog circuits are outlined.

The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes

As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra–high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.

http://science.sciencemag.org/content/sci/341/6146/640.full.pdf

A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation

As the dimension of the metal oxide semiconductor field effect transistor (MOSFET) keeping scaling, the short channel effects are becoming serious problems. Recently a MOS-based vertical tunneling transistor in silicon was proposed as a possible successor of the MOSFET. In this work, the device simulation of this novel transistor is performed in order to investigate the impacts of doping profile, gate oxide thickness and drain doping level on the device performance. The simulation shows that the sharp doping profile, thin gate oxide thickness and high drain doping level are the key technologies for fabricating the high performance Esaki-tunneling FET. Finally, the optimized device with high performance is proposed.

Peng-Fei Wang

Papers

Complementary tunneling transistor for low power application

Design of U-Shape Channel Tunnel FETs With SiGe Source Regions

The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes

A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation

Simulation of the Esaki-tunneling FET