Pengfei Guo

Bio: Pengfei Guo is an academic researcher from National University of Singapore. The author has contributed to research in topics: Germanium & Transistor. The author has an hindex of 16, co-authored 42 publications receiving 1093 citations.

Tunneling Field-Effect Transistor: Capacitance Components and Modeling

Abstract: We report a numerical simulation study of gate capacitance components in a tunneling field-effect transistor (TFET), showing key differences in the partitioning of gate capacitance between the source and drain as compared with a MOSFET. A compact model for TFET capacitance components, including parasitic and inversion capacitances, was built and calibrated with computer-aided design data. This model should be useful for further investigation of performance of circuits containing TFETs. The dependence of gate-drain capacitance Cgd on drain design and gate length was further investigated for reduction of switching delay in TFETs.

Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current

Abstract: We report the first study of the effect of strain on tunneling field-effect transistor (TFET) characteristics. Double-gate silicon TFETs were employed. It was found that tensile strain increases the drain current, whereas compressive strain reduces the drain current. This is attributed to strain-induced band splitting and carrier repopulation and provides guidelines on strain engineering of TFETs. An elaborate study of the dependence of the electrical characteristics of TFET on temperature is also reported. It was observed that on-state tunneling current exhibits a positive temperature dependence at low drain bias condition (V DS = 1 V), whereas opposite behavior was observed when V DS = 1.5 V. When the device temperature is increased, enhancement of the drain current at V DS = 1 V results from band gap narrowing, whereas reduction in the drain current at V DS = 1.5 V is attributed to the decrease in the electric field at the tunneling junction.

High-mobility germanium-tin (GeSn) P-channel MOSFETs featuring metallic source/drain and sub-370 °C process modules

Abstract: We report the first demonstration of GeSn pMOSFETs. Key highlights of this work also includes a 180 °C GeSn MBE growth, sub-370 °C Si 2 H 6 surface passivation and gate stack process for GeSn, and an implantless metallic NiGeSn S/D formed at 350 °C. A hole mobility of 430 cm2/Vs is obtained for GeSn pMOSFETs, which is 66% higher than that of the Ge control pMOSFETs. GeSn pMOSFETs show a 64% lower S/D resistance as compared to the Ge control devices.

Germanium–Tin (GeSn) p-Channel MOSFETs Fabricated on (100) and (111) Surface Orientations With Sub-400 $^{\circ}\hbox{C}\ \hbox{Si}_{2}\hbox{H}_{6}$ Passivation

Abstract: In this letter, we report the first study of the dependence of carrier mobility and drive current IDsat of Ge0.958Sn0.042 p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) on surface orientations. Compressively strained Ge0.958Sn0.042 channels were grown on (100) and (111) Ge substrates. Sub-400°C Si2H6 treatment was introduced for the passivation of the GeSn surface prior to gate stack formation. Source/ drain series resistance and subthreshold swing S were found to be independent of surface orientation. The smallest reported S of 130 mV/decade for GeSn pMOSFETs is achieved. The (111)-oriented device demonstrates 13% higher IDsat over the (100)oriented one at a VGS-VTH of -0.6 V and VDS of -0.9 V. We also found that GeSn pMOSFETs with (111) surface orientation show 18% higher hole mobility than GeSn pMOSFETs with (100) orientation.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Tunnel Field-Effect Transistors: State-of-the-Art

Abstract: Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/ \({{\mu }}\) m. A common approach to TFET characterization is proposed to facilitate future comparisons.

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

Abstract: In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs

Abstract: Germanium is a widely used material for tunnel FETs because of its small band gap and compatibility with silicon. Typically, only the indirect band gap of Ge at 0.66 eV is considered. However, direct band-to-band tunneling (BTBT) in Ge should be included in tunnel FET modeling and simulations since the energy difference between the Ge conduction band edges at the L and Γ valleys is only 0.14 eV at room temperature. In this paper, we theoretically calculate the parameters A and B of Kane's direct and indirect BTBT models at different tunneling directions ([100], [110], and [111]) for Si, Ge and unstrained Si1-xGex. We highlight how the direct BTBT component becomes more important as the Ge mole fraction increases. The calculation of the band-to-band generation rate in the uniform electric field limit reveals that direct tunneling always dominates over indirect tunneling in Ge. The impact of the direct transition in Ge on the performance of two realistic tunnel field-effect transistor configurations is illustrated with TCAD simulations. The influence of field-induced quantum confinement is included in the analysis based on a back-of-the-envelope calculation.

Vertical Si-Nanowire $n$ -Type Tunneling FETs With Low Subthreshold Swing ( $\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature

Abstract: This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioff ratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.