Pervez M. Aziz

Bio: Pervez M. Aziz is an academic researcher from LSI Corporation. The author has contributed to research in topics: Signal & Phase detector. The author has an hindex of 19, co-authored 71 publications receiving 1934 citations. Previous affiliations of Pervez M. Aziz include Agere Systems & Avago Technologies.

An overview of sigma-delta converters

Abstract: Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

An Overview of Sigma-Delta Converters: How a 1-bit ADC achieves more than 16-bit resolution

Abstract: This article briefly describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. Next, we examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

Abstract: A high-speed SerDes must meet multiple challenges including high-speed operation, intensive equalization technique, low power consumption, small area and robustness. In order to meet new standards, such a OIF CEI-25G-LR, CEI-28G-MR/SR/VSR, IEEE802.3bj and 32G-FC, data-rates are increased to 25 to 28Gb/s, which is more than 75% higher than the previous generation of SerDes. For SerDes applications with several hundreds of lanes integrated in single chip, power consumption is very important factor while maintaining high performance. There are several previous works at 28Gb/s or higher data-rate [1-2]. They use an unrolled DFE to meet the critical timing margin, but the unrolled DFE structure increases the number of DFE slicers, increasing the overall power and die area. In order to tackle these challenges, we introduce several circuits and architectural techniques. The analog front-end (AFE) uses a single-stage architecture and a compact on-chip passive inductor in the transimpedance amplifier (TIA), providing 15dB boost. The boost is adaptive and its adaptation loop is decoupled from the decision-feedback equalizer (DFE) adaptation loop by the use of a group-delay adaptation (GDA) algorithm. DFE has a half-rate 1-tap unrolled structure with 2 total error latches for power and area reduction. A two-stage sense-amplifier-based slicer achieves a sensitivity of 15mV and DFE timing closure. We also develop a high-speed clock buffer that uses a new active-inductor circuit. This active-inductor circuit has the capability to control output-common-mode voltage to optimize circuit operating points.

Servo data detection in the presence or absence of radial incoherence using digital interpolators

Abstract: Techniques for detecting data, such as servo data, from input or incoming data read from a transmission medium, such as magnetic recording medium, in the presence or absence of radial incoherence. In one illustrative recording medium-based aspect of the invention, such a technique for detecting data from input data stored on a recording medium comprises the following steps. First, one or more samples are interpolated from one or more samples which have been generated from the input data at a given symbol rate. The one or more interpolated samples have one or more phases associated therewith which differ from a phase associated with the one or more samples generated at the given symbol rate. Then, an optimum or best phase is selected from the symbol rate phase and the one or more interpolated phases such that at least a portion of the one or more samples associated with the optimum phase are identified as representative of detected data.

A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS

Abstract: A robust transceiver designed for NRZ signaling beyond 10Gb/s over long-range physical media (including electrical backplanes, copper cables and optical modules) must contend with significant challenges from insertion loss, crosstalk, and reflection. For inter-symbol interference (ISI) cancellation, half-rate decision-feedback equalizer (DFE) with unrolled first tap [1–3] is widely used to avoid noise amplification and to relax timing for data sampling/feedback. However, tap-unrolling increases slicer count and entails half-rate multiplexers eating into timing margin. To remove reflection-induced ISI due to impedance discontinuities in the media, the DFE must cover tap positions higher than 30UI which is beyond tap range of the DFEs reported in previous work [1–4]. Fig. 1 shows an example of bumpy channel with reflection energy up to 40UI.

A wavelet tour of signal processing

Abstract: Introduction to a Transient World. Fourier Kingdom. Discrete Revolution. Time Meets Frequency. Frames. Wavelet Zoom. Wavelet Bases. Wavelet Packet and Local Cosine Bases. An Approximation Tour. Estimations are Approximations. Transform Coding. Appendix A: Mathematical Complements. Appendix B: Software Toolboxes.

Multirate digital signal processing

Abstract: There has been a great deal of material in the area of discrete-time transforms that has been published in recent years. This book does an excellent job of presenting important aspects of such material in a clear manner. The book has 11 chapters and a very useful appendix. Seven of these chapters are essentially devoted to the Fourier series/transform, discrete Fourier transform, fast Fourier transform (FFT), and applications of the FFT in the area of spectral estimation. Chapters 8 through 10 deal with many other discrete-time transforms and algorithms to compute them. Of these transforms, the KarhunenLoeve, the discrete cosine, and the Walsh-Hadamard transform are perhaps the most well-known. A lucid discussion of number theoretic transforms i5 presented in Chapter 11. This reviewer feels that the authors have done a fine job of compiling the pertinent material and presenting it in a concise and clear manner. There are a number of problems at the end of each chapter, an appreciable number of which are challenging. The authors have included a comprehensive set of references at the end of the book. In brief, this book is a valuable contribution to the general areas of signal processing and communications. It can be used for a graduate level course in perhaps two ways. One would be to cover the first seven chapters in great detail. The other would be to cover the whole book by focussing on different topics in a selective manner. This book by Elliott and Rao is extremely useful to researchers/engineers who are working in the areas of signal processing and communications. It i s also an excellent reference book, and hence a valuable addition to one’s library

1-Bit compressive sensing

Abstract: Compressive sensing is a new signal acquisition technology with the potential to reduce the number of measurements required to acquire signals that are sparse or compressible in some basis. Rather than uniformly sampling the signal, compressive sensing computes inner products with a randomized dictionary of test functions. The signal is then recovered by a convex optimization that ensures the recovered signal is both consistent with the measurements and sparse. Compressive sensing reconstruction has been shown to be robust to multi-level quantization of the measurements, in which the reconstruction algorithm is modified to recover a sparse signal consistent to the quantization measurements. In this paper we consider the limiting case of 1-bit measurements, which preserve only the sign information of the random measurements. Although it is possible to reconstruct using the classical compressive sensing approach by treating the 1-bit measurements as plusmn 1 measurement values, in this paper we reformulate the problem by treating the 1-bit measurements as sign constraints and further constraining the optimization to recover a signal on the unit sphere. Thus the sparse signal is recovered within a scaling factor. We demonstrate that this approach performs significantly better compared to the classical compressive sensing reconstruction methods, even as the signal becomes less sparse and as the number of measurements increases.

An overview of sigma-delta converters

Abstract: Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

Robust 1-Bit Compressive Sensing via Binary Stable Embeddings of Sparse Vectors

Abstract: The compressive sensing (CS) framework aims to ease the burden on analog-to-digital converters (ADCs) by reducing the sampling rate required to acquire and stably recover sparse signals. Practical ADCs not only sample but also quantize each measurement to a finite number of bits; moreover, there is an inverse relationship between the achievable sampling rate and the bit depth. In this paper, we investigate an alternative CS approach that shifts the emphasis from the sampling rate to the number of bits per measurement. In particular, we explore the extreme case of 1-bit CS measurements, which capture just their sign. Our results come in two flavors. First, we consider ideal reconstruction from noiseless 1-bit measurements and provide a lower bound on the best achievable reconstruction error. We also demonstrate that i.i.d. random Gaussian matrices provide measurement mappings that, with overwhelming probability, achieve nearly optimal error decay. Next, we consider reconstruction robustness to measurement errors and noise and introduce the binary e-stable embedding property, which characterizes the robustness of the measurement process to sign changes. We show that the same class of matrices that provide almost optimal noiseless performance also enable such a robust mapping. On the practical side, we introduce the binary iterative hard thresholding algorithm for signal reconstruction from 1-bit measurements that offers state-of-the-art performance.