Peter Hazucha

Bio: Peter Hazucha is an academic researcher from Intel. The author has contributed to research in topics: Inductor & CMOS. The author has an hindex of 27, co-authored 81 publications receiving 3024 citations.

Area-efficient linear regulator with ultra-fast load regulation

Abstract: We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

Abstract: We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

Abstract: The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area The measured SER per bit of SRAMs in 025 /spl mu/m, 018 /spl mu/m, 013 /spl mu/m, and 90 nm showed an increase of 8% per generation

A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

Abstract: We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a 90-nm CMOS process, employing a four-phase hysteretic control, and operating at ultra-high frequency of 480-MHz, we achieved a 10% output droop with only 2.5 nF of on-chip decoupling, for 0.5 A of load current. No off-chip decoupling was connected to the output. At 480 MHz the measured efficiency was 72%. At 250 MHz, the efficiency improved to 76% at the cost of a 17% droop or larger decoupling of 11.5 nF. A converter with 100 A rating would require a capacitor of 0.5 /spl mu/F, which is comparable to the size of an on-chip capacitor of a typical microprocessor.

Integrated on-chip inductors using magnetic material (invited)

Abstract: On-chip inductors with magnetic material are integrated into both advanced 130 and 90 nm complementary metal-oxide semiconductor processes. The inductors use aluminum or copper metallization and amorphous CoZrTa magnetic material. Increases in inductance of up to 28 times corresponding to inductance densities of up to 1.3 μ H / mm 2 were obtained, significantly greater than prior values for on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. The CoZrTa was chosen for its good combination of high permeability, good high-temperature stability ( > 250 ° C ) , high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The CoZrTa alloy can operate at frequencies up to 9.8 GHz , but trade-offs exist between frequency, inductance, and quality factor. The effects of increasing the magnetic thickness on the permeability spectra were measured and modeled. The inductors use magnetic vias and elongated structures to take advantage of the uniaxial magnetic anisotropy. Techniques are presented to extract a sheet inductance and examine the effects of magnetic vias on the inductors. The inductors with thick copper and thicker magnetic films have resistances as low as 0.04 Ω , and quality factors up to 8 at frequencies as low as 40 MHz.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

Abstract: As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Multiresonant Frequency-Locked Loop for Grid Synchronization of Power Converters Under Distorted Grid Conditions

Abstract: This paper presents a new multiresonant frequency-adaptive synchronization method for grid-connected power converters that allows estimating not only the positive- and negative-sequence components of the power signal at the fundamental frequency but also other sequence components at other harmonic frequencies. The proposed system is called MSOGI-FLL since it is based on both a harmonic decoupling network consisting of multiple second-order generalized integrators (MSOGIs) and a frequency-locked loop (FLL), which makes the system frequency adaptive. In this paper, the MSOGI-FLL is analyzed for single- and three-phase applications, deducing some key expressions regarding its stability and tuning. Moreover, the performance of the MSOGI-FLL is evaluated by both simulations and experiments to show its capability for detecting different harmonic components in a highly polluted grid scenario.

System level analysis of fast, per-core DVFS using on-chip switching regulators

Abstract: Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order of tens of microseconds. In addition, the recent trend towards chip-multiprocessors (CMP) executing multi-threaded workloads with heterogeneous behavior motivates the need for per-core DVFS control mechanisms. Voltage regulators that are integrated onto the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and per-core voltage control. We show that these characteristics provide significant energy-saving opportunities compared to traditional off-chip regulators. However, the implementation of on-chip regulators presents many challenges including regulator efficiency and output voltage transient characteristics, which are significantly impacted by the system-level application of the regulator. In this paper, we describe and model these costs, and perform a comprehensive analysis of a CMP system with on-chip integrated regulators. We conclude that on-chip regulators can significantly improve DVFS effectiveness and lead to overall system energy savings in a CMP, but architects must carefully account for overheads and costs when designing next-generation DVFS systems and algorithms.

Robust system design with built-in soft-error resilience

Abstract: Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A system's susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.

Characterization of soft errors caused by single event upsets in CMOS processes

Abstract: Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.