P
Ph. Galy
Researcher at STMicroelectronics
Publications - 50
Citations - 355
Ph. Galy is an academic researcher from STMicroelectronics. The author has contributed to research in topics: CMOS & Electrostatic discharge. The author has an hindex of 10, co-authored 50 publications receiving 308 citations. Previous affiliations of Ph. Galy include IT University & Université de Sherbrooke.
Papers
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Journal ArticleDOI
A review of the Z 2 -FET 1T-DRAM memory: Operation mechanisms and key parameters
Sorin Cristoloveanu,Kyung Hwa Lee,Mukta Singh Parihar,H. El Dirani,H. El Dirani,Joris Lacord,Sebastien Martinie,C. Le Royer,J.-Ch. Barbe,X. Mescot,Pascal Fonteneau,Ph. Galy,Francisco Gamiz,Carlos Navarro,Binjie Cheng,M. Duan,Fikru Adamu-Lema,Asen Asenov,Yuan Taur,Yong Xu,Yong Tae Kim,Jing Wan,M. Bawedin +22 more
TL;DR: The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory, which offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed, is reviewed.
Proceedings ArticleDOI
BIMOS transistor and its applications in ESD protection in advanced CMOS technology
Ph. Galy,Jean Jimenez,Johan Bourgeat,Alexandre Dray,Ghislain Troussier,Boris Heitz,Nicolas Guitard,D. Marin-Cudraz,H. Beckrich-Ros +8 more
TL;DR: This paper introduces the BIMOS ESD approach with simulations in 45nm with Silicon measurements performed on 32 nm CMOS high k metal gate.
Proceedings ArticleDOI
Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing
B. Cardoso Paz,L. Le Guevel,M. Casse,Gerard Billiot,Gael Pillonnet,A. G. M. Jansen,Romain Maurand,Sebastien Haendler,Andre Juge,Emmanuel Vincent,Ph. Galy,Gerard Ghibaudo,M. Vinet,S. De Franceschi,T. Meunier,F. Gaillard +15 more
TL;DR: In this article, the performance of 28nm FD-SOI transistors was evaluated for the first time down to ultra low temperatures (UL T), at T = 1 00mK.
Journal ArticleDOI
Evidence of Supercoupling Effect in Ultrathin Silicon Layers Using a Four-Gate MOSFET
TL;DR: In this paper, the supercoupling effect was demonstrated experimentally by monitoring the electron and hole currents in a field-effect transistor provided with p ≥ 0 and n ≥ 0 contacts.
Proceedings Article
ESD design challenges in 28nm hybrid FDSOI/Bulk advanced CMOS process
Alexandre Dray,Nicolas Guitard,Pascal Fonteneau,Dominique Golanski,C. Fenouillet-Beranger,H. Beckrich,Radhakrishnan Sithanandam,T. Benoist,Charles-Alexandre Legrand,Ph. Galy +9 more
TL;DR: In this paper, an innovative way to design competitive ESD protection networks in advanced FDSOI CMOS technology thanks to Hybrid Bulk co-integration is presented, and an optimal placement of elementary ESD devices is discussed and their ESD performances are compared.