Biological cells are characterized by highly complex phenomena and processes that are, to a great extent, interdependent. To gain detailed insights, devices designed to study cellular phenomena need to enable tracking and manipulation of multiple cell parameters in parallel; they have to provide high signal quality and high-spatiotemporal resolution. To this end, we have developed a CMOS-based microelectrode array system for in vitro applications that integrates six measurement and stimulation functions, the largest number to date. Moreover, the system features the largest active electrode array area to date ( $4.48 \times 2.43$ mm2) to accommodate 59 760 electrodes, while its power consumption, noise characteristics, and spatial resolution (13.5- $\mu$ m electrode pitch) are comparable to the best state-of-the-art devices. The system includes: 2048 action potential (AP, bandwidth: 300 Hz–10 kHz) recording units, 32 local-field-potential (LFP, bandwidth: 1 Hz–300 Hz) recording units, 32 current recording units, 32 impedance measurement units, and 28 neurotransmitter detection units, in addition to the 16 dual-mode voltage-only or current/voltage-controlled stimulation units. The electrode array architecture is based on a switch matrix, which allows for connecting any measurement/stimulation unit to any electrode in the array and for performing different measurement/stimulation functions in parallel.

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In Vitro Multi-Functional Microelectrode Array Featuring 59 760 Electrodes, 2048 Electrophysiology Channels, Stimulation, Impedance Measurement, and Neurotransmitter Detection Channels

A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm2 chip was fabricated in a standard 0.16 μm CMOS process.

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A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset

This disclosure describes a chopper-stabilized sigma-delta analog-to-digital converter (ADC). The ADC is configured to provide accurate output at low frequency with relatively low power. The chopper-stabilized ADC substantially reduces or eliminates noise and offset from an output signal produced by the mixer amplifier. Dynamic limitations, i.e., glitching that result from chopper stabilization at low power are substantially eliminated or reduced through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the ADC operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. In this manner, the chopper-stabilized ADC can be used in a low power system, such as an implantable medical device (IMD), to provide a stable, low-noise output signal.

Chopper-stabilized analog-to-digital converter

A calibration-free, high-resolution analog-to-digital converter designed for a bioluminescence sensor array employs incremental sigma-delta (ΣΔ) modulation to combine the advantages of oversampling with an input multiplexing capability. The resolution of incremental ΣΔ modulators can be improved significantly by means of a technique similar to extended counting. In the approach proposed in this paper, analog-to-digital conversion is accomplished with a two-step process in which the residual error from a second-order incremental ΣΔ modulator is encoded using a successive approximation ADC. By this means it is possible to achieve enhanced resolution and improved static linearity while maintaining a one-to-one mapping between individual input and output samples. An experimental implementation of the proposed modulator has been integrated in a 0.18-μm CMOS technology. Operating from a 1.8-V supply, it achieves a dynamic range of 90.1 dB and a peak signal-to-noise and distortion ratio (SNDR) of 86.3 dB at a conversion rate of 1 MSample/s, with 38.1-mW power consumption.

A High-Resolution Low-Power Incremental $\Sigma\Delta$ ADC With Extended Range for Biosensor Arrays

MEMS-based oscillators offer a silicon-based alternative to quartz-based frequency references. Here, a MEMS-based programmable oscillator is presented which achieves better than ±0.5-ppm frequency stability from -40°C to 85°C and less than 1-ps (rms) integrated phase noise (12 kHz to 20 MHz). A key component of this system is a thermistor-based temperature-to-digital converter (TDC) which enables accurate and low noise compensation of temperature-induced variation of the MEMS resonant frequency. The TDC utilizes several circuit techniques including a high-resolution tunable reference resistor based on a switched-capacitor network and fractional-N frequency division, a switched resistor measurement approach which allows a pulsed bias technique for reduced noise, and a VCO-based quantizer for digitization of the temperature signal. The TDC achieves 0.1-mK (rms) resolution within a 5-Hz bandwidth while consuming only 3.97 mA for all analog and digital circuits at 3.3-V supply in 180-nm CMOS.

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With $ Frequency Stability and $ Integrated Jitter

This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 muVRMS), the DC offset 2 muV, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 muA current during conversion

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A low-power 22-bit incremental ADC

An over-sampling analog-to-digital converter (ADC) uses a chopper stabilized voltage reference with improved reference voltage offset cancellation and reduced source induced 1/f noise. The chopper stabilized voltage reference receives chopper clocks that have been correlated with the serial bitstream produced by the sigma-delta modulator of the ADC. The chopper clocks are generated so that the reference voltage produces for each distinct bitstream level an independent sequence of voltages that comprise alternatively positive and negative voltage reference offset contributions. After integration (averaging) is performed within the sigma-delta modulator, these equal and opposite reference offset contributions cancel out regardless of the bit pattern comprising the bitstream.

Offset Cancellation and Reduced Source Induced 1/F Noise of Voltage Reference by Using Bit Stream From Over-Sampling Analog-to-Digital Converter

In this paper the theoretical operation of incremental (charge-balancing) delta-sigma (DeltaSigma) converters is reviewed, and the implementation of a 22-bit incremental A/D converter is described. Two different analyses of the first-order incremental converter are presented, and based on these results two extensions to higher-order modulators are proposed. Since line-frequency noise suppression is often important in measurement applications, modulators followed by sinck filters are also analyzed. Equations are derived for the estimation of the required number of cycles for a given resolution and architecture. Finally, the design and implementation of a third-order incremental converter with a fourth-order sine filter is briefly discussed

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Incremental Delta-Sigma Structures for DC Measurement: an Overview

A five-level feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta analog-to-digital converter has an improved switching sequence that boosts from two to five the number of quantization levels of the feed-back DAC. Switching sequences are used to obtain five equally distributed charge levels C * VREF, C * VREF/2, 0, -C * VREF/2 and -C * VREF. When summed with an input voltage, VIN, the five-level feed­back DAC produces five equally distributed output voltages of A * VIN + VREF, A * VIN + VREF/2, A * VIN + 0, A * VIN - VREF/2 and A * VIN - VREF, where A is gain, VIN is the input voltage, and VREF is the reference voltage.

Five-level feed-back digital-to-analog converter for a switched capacitor sigma-delta analog-to-digital converter

A multi-bit digital-to-analog converter has a reference voltage generator generating a reference voltage with an offset voltage; a.switched capacitor stage for generating a plurality of output voltages; and a switching sequencer controlling the switched capacitor stage operable to generate switching patterns for each output voltages, wherein each pattern has a charge phase and a transfer phase, and wherein for at least one output voltage the switching sequencer provides two switching patterns wherein each switching pattern contributes an offset of opposite polarity.

Philippe Deval

Papers

A low-power 22-bit incremental ADC

Offset Cancellation and Reduced Source Induced 1/F Noise of Voltage Reference by Using Bit Stream From Over-Sampling Analog-to-Digital Converter

Incremental Delta-Sigma Structures for DC Measurement: an Overview

Five-level feed-back digital-to-analog converter for a switched capacitor sigma-delta analog-to-digital converter

Multi-level feed-back digital-to-analog converter using a chopper voltage reference for a switched capacitor sigma-delta analog-to-digital converter