For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers. The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels.

CMOS VLSI Design : A Circuits and Systems Perspective

A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g/sub m//I/sub D/ and the normalized current I/sub D//(W/L). The g/sub m//I/sub D/ indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).

A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

A simple cascode with the gate voltage of the cascode transistor being controlled by a feedback amplifier called a regulated cascode is presented. In comparison to the standard cascode circuit, the minimum output voltage is lower by about 30 to 60% while the output conductance and the feedback capacitance are lower by about 100 times. An analytical large-signal, small-signal, and noise analysis is carried out. Some applications like current mirrors and voltage amplifiers are discussed. Experimental results confirming the theory are presented. >

A high-swing, high-impedance MOS cascode circuit

We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method, therefore, yields completely automated sizing of (globally) optimal CMOS amplifiers, directly from specifications. In this paper, we apply this method to a specific widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can he used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.

/pdf/optimal-design-of-a-cmos-op-amp-via-geometric-programming-4thsejbwi6.pdf

Optimal design of a CMOS op-amp via geometric programming

A charge pump cell is used to make a voltage doubler using improved serial switches. A complete power efficiency theory is presented which fits the measurements. The importance of capacitors is shown with plots of power efficiency versus load and stray capacitors. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. A power efficiency of 95% has been reached using external capacitors. A fully integrated charge pump is also presented and shows a maximum power efficiency of 75%.

A high-efficiency CMOS voltage doubler

1.1 ANALOG INTEGRATED CIRCUIT DESIGN 1.2 NOTATION, SYMBOLOGY AND TERMINOLOGY 1.3 ANALOG SIGNAL PROCESSING 1.4 EXAMPLE OF ANALOG VLSI MIXED-SIGNAL CIRCUIT DESIGN 2.1 BASIC MOS SEMICONDUCTOR FABRICATION PROCESSES 2.2 THE PN JUNCTION 2.3 THE MOS TRANSISTOR 2.4 PASSIVE COMPONENTS 2.5 OTHER CONSIDERATIONS OF CMOS TECHNOLOGY 3.1 SIMPLE MOS LARGE-SIGNAL MODEL (SPICE LEVEL 1) 3.2 OTHER MOS LARGE-SIGNAL MODEL PARAMETERS 3.3 SMALL-SIGNAL MODEL FOR THE MOS TRANSISTOR 3.4 COMPUTER SIMULATION MODELS 3.5 SUBTHRESHOLD MOS MODEL 3.6 SPICE SIMULATION OF MOS CIRCUITS 4.1 MOS SWITCH 4.2 MOS DIODE/ACTIVE RESISTOR 4.3 CURRENT SINKS AND SOURCES 4.4 CURRENT MIRRORS 4.5 CURRENT AND VOLTAGE REFERENCES 4.6 BANDGAP REFERENCE 5.1 INVERTERS 5.2 DIFFERENTIAL AMPLIFIERS 5.3 CASCODE AMPLIFIERS 5.4* CURRENT AMPLIFIERS 5.5* OUTPUT AMPLIFIERS/BUFFERS 6.1 DESIGN OF CMOS OP AMPS 6.2 COMPENSATION OF OP AMP 6.3 DESIGN OF TWO-STAGE OP AMPS 6.4 POWER-SUPPLY REJECTION RATIO OF TWO-STAGE OP AMPS 6.5 CASCODE OP AMPS 6.6 SIMULATION AND MEASUREMENT OF OP AMPS 6.7 MACROMODELS FOR OP AMPS 7.1 BUFFERED OP AMPS 7.2 HIGH-SPEED/FREQUENCY OP AMPS 7.3 DIFFERENTIAL-OUTPUT OP AMPS 7.4 MICROPOWER OP AMPS 7.5 LOW NOISE OP AMPS 7.6 LOW VOLTAGE OP AMPS 8.1 CHARACTERIZATION OF A COMPARATOR 8.2 TWO-STAGE, OPEN-LOOP COMPARATOR DESIGN 8.3 OTHER OPEN-LOOP COMPARATORS 8.4 IMPROVING THE PERFORMANCE OF OPEN-LOOP COMPARATORS 8.5 DISCRETE-TIME COMPARATORS 8.6 HIGH-SPEED COMPARATORS APPENDIX A CIRCUIT ANALYSIS FOR ANALOG CIRCUIT DESIGN APPENDIX B INTEGRATED CIRCUIT LAYOUT APPENDIX C CMOS DEVICE CHARACTERIZATION APPENDIX D TIME AND FREQUENCY DOMAIN RELATIONSHIP FOR SECOND-ORDER SYSTEMS

CMOS Analog Circuit Design

VLSI Design Techniques for Analog and Digital Circuits

Introduction to the theory and design of active filters

A method of designing continuous-time active RC filters which employ only capacitors and FET transistors is presented. The effective RC time constants of these filters are determined by capacitor ratios. The filters employ switched resistors. These filters can use any existing active RC or passive RC topology as the basis for the design and inherit the sensitivity properties of the circuit from which they are derived. These switched-resistor (SR) filters operate over a wide frequency range and are manufacturable in monolithic form using a basic MOS process which requires no component trimming.

http://class.ece.iastate.edu/vlsi2/docs/papers done/1982-05-tcas1-pa.pdf

Switched-resistor filters-A continuous time approach to monolithic MOS filter design

Methods applicable to teaching microelectronics at the undergraduate and graduate level in conjunction with an industrial fabrication capability are presented. Results of three semesters of teaching microelectronics at the graduate level with emphasis on both digital and analog circuits are summarized. Plans for teaching an undergraduate course utilizing the fabrication of integrated circuits are discussed.

/pdf/graduate-and-undergraduate-educational-methods-for-4yr7jx8rj3.pdf

Phillip E Allen

Papers

CMOS Analog Circuit Design

VLSI Design Techniques for Analog and Digital Circuits

Introduction to the theory and design of active filters

Switched-resistor filters-A continuous time approach to monolithic MOS filter design

Graduate and Undergraduate Educational Methods for Microelectronics