Phrangboklang Lyngton Thangkhiew

Bio: Phrangboklang Lyngton Thangkhiew is an academic researcher from National Institute of Technology, Meghalaya. The author has contributed to research in topics: Memristor & Crossbar switch. The author has an hindex of 7, co-authored 10 publications receiving 132 citations.

A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar

Abstract: Because of their resistive switching properties and ease of controlling the resistive states, memristors have been proposed in nonvolatile storage as well as logic design applications. Memristors can be fabricated in a crossbar and suitable voltages applied to the row and column nanowires to control their states. This makes it possible to move toward new non-von Neumann-type architectures, usually referred to as in-memory computing, where logic operations can be performed directly on the storage fabric. In this paper, a scalable design flow for in-memory computing has been proposed, where a given multioutput logic function is synthesized as a netlist of NOT/NOR gates and then mapped to the crossbar using the Memristor-Aided loGIC (MAGIC) design style. The memristors corresponding to the primary inputs are initialized a priori. Subsequently, the required gate operations are performed by applying suitable row and column voltages in sequence. Two alternate mapping schemes have been analyzed. The switching characteristics of MAGIC NOR gates have been evaluated using circuit simulation under the Cadence Virtuoso environment. Experimental evaluation on ISCAS'85 benchmarks reports the average improvements of 27.7%, 34.6%, and 26.2%, respectively over a recently published work with respect to the number of memristors, number of cycles, and total energy dissipation, respectively. It may be noted that the energy consumption of the gates used in the proposed approach (NOT and NOR) is significantly higher than that using CMOS technology.

Efficient Mapping of Boolean Functions to Memristor Crossbar Using MAGIC NOR Gates

Abstract: Memristor is considered as a promising circuit element which can be used in many applications. Various synthesis methods for Boolean functions have been explored in the literature using memristor-based design styles. Memristor crossbar is considered as one of the most preferred structures for implementing logic functions as well as memory. In this paper, a general synthesis flow has been proposed using the MAGIC logic design style to map multioutput Boolean functions to memristor crossbars. The functions are realized as a netlist of NOR and NOT gates. Two alternate methods of evaluating the gates are used, serial and parallel, which give a tradeoff between the number of cycles and the size of the crossbar. A strategy for scheduling the gates to time steps has also been proposed to reduce the hardware overhead. The switching delays and energy requirements are estimated using SPICE simulation. Synthesis results are reported for ISCAS’85 benchmark functions that show an average reduction of 68.8% in the number of cycles, 52.8% in energy consumption, and 96.4% in the number of memristors required as compared to a very recently published work.

Area efficient implementation of ripple carry adder using memristor crossbar arrays

Abstract: Memristor has drawn the attention of circuit designers for its non-volatility, and is considered as a viable candidate to replace CMOS technology in many applications. Another interesting characteristic of memristor is that it can be employed in crossbar array architecture that allows very high packing density. In addition to implementing high capacity storage systems, memristor can also be used to realize logic functions. In this paper, the Memristor Aided Logic (MAGIC) design style is used to map the NOR netlist of a given Boolean function to memristor crossbar arrays. Various optimization techniques have been used by scheduling the NOR gates to time steps in order to reduce the hardware cost. To illustrate the viability of the design methodology, full adder and ripple carry adder circuits have been studied and analyzed.

Neuromemristive Circuits for Edge Computing: A Review

Abstract: The volume, veracity, variability, and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks, and open problems in the field of neuromemristive circuits for edge computing.

High Level Synthesis Introduction To Chip And System Design

Abstract: Thank you very much for downloading high level synthesis introduction to chip and system design. Maybe you have knowledge that, people have look hundreds times for their favorite books like this high level synthesis introduction to chip and system design, but end up in harmful downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they cope with some infectious bugs inside their desktop computer.

A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar

Abstract: Because of their resistive switching properties and ease of controlling the resistive states, memristors have been proposed in nonvolatile storage as well as logic design applications. Memristors can be fabricated in a crossbar and suitable voltages applied to the row and column nanowires to control their states. This makes it possible to move toward new non-von Neumann-type architectures, usually referred to as in-memory computing, where logic operations can be performed directly on the storage fabric. In this paper, a scalable design flow for in-memory computing has been proposed, where a given multioutput logic function is synthesized as a netlist of NOT/NOR gates and then mapped to the crossbar using the Memristor-Aided loGIC (MAGIC) design style. The memristors corresponding to the primary inputs are initialized a priori. Subsequently, the required gate operations are performed by applying suitable row and column voltages in sequence. Two alternate mapping schemes have been analyzed. The switching characteristics of MAGIC NOR gates have been evaluated using circuit simulation under the Cadence Virtuoso environment. Experimental evaluation on ISCAS'85 benchmarks reports the average improvements of 27.7%, 34.6%, and 26.2%, respectively over a recently published work with respect to the number of memristors, number of cycles, and total energy dissipation, respectively. It may be noted that the energy consumption of the gates used in the proposed approach (NOT and NOR) is significantly higher than that using CMOS technology.

SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput

Abstract: In-memory processing can dramatically improve the latency and energy consumption of computing systems by minimizing the data transfer between the memory and the processor. Efficient execution of processing operations within the memory is therefore, a highly motivated objective in modern computer architecture. This article presents a novel automatic framework for efficient implementation of arbitrary combinational logic functions within a memristive memory. Using tools from logic design, graph theory and compiler register allocation technology, we developed synthesis and in-memory mapping of logic execution in a single row (SIMPLER), a tool that optimizes the execution of in-memory logic operations in terms of throughput and area. Given a logical function, SIMPLER automatically generates a sequence of atomic memristor-aided logic (MAGIC) NOR operations and efficiently locates them within a single size-limited memory row, reusing cells to save area when needed. This approach fully exploits the parallelism offered by the MAGIC NOR gates. It allows multiple instances of the logic function to be performed concurrently, each compressed into a single row of the memory. This virtue makes SIMPLER an attractive candidate for designing in-memory single instruction, multiple data (SIMD) operations. Compared to the previous work (that optimizes latency rather than throughput for a single function), SIMPLER achieves an average throughput improvement of $435\times $ . When the previous tools are parallelized similarly to SIMPLER, SIMPLER achieves higher throughput of at least $5\times $ , with $23\times $ improvement in area and $20\times $ improvement in area efficiency. These improvements more than fully compensate for the increase (up to 17% on average) in latency.

Reconfigurable Boolean Logic in Memristive Crossbar: The Principle and Implementation

Abstract: In-memory computing based on memristive logic is considered as a prospective non von Neumann computing paradigm. In this letter, we systematically analyze the four-variable logic method and map it into the operation of two anti-serial complementary memristors in the crossbar array architecture. Arbitrary Boolean logic can be implemented within three cycles with the experimental evidence of reconfigurable NAND, NOR, and XOR logic using Pt/HfO2/TiN devices. Taking advantage of the functional flexibility, a parallel 1-bit full adder that can be realized in 8 cycles within a $\textsf {4}\times \textsf {3}$ array has been designed and verified in simulation.