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Author

Pierre Lefranc

Bio: Pierre Lefranc is an academic researcher from University of Grenoble. The author has contributed to research in topics: Gate driver & Power semiconductor device. The author has an hindex of 8, co-authored 39 publications receiving 244 citations.

Papers
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Journal ArticleDOI
TL;DR: In this paper, a specific architecture for a low-side/high-side gate driver implementation for power devices running at high switching frequencies and under very high switching speeds is presented.
Abstract: This paper presents a specific architecture for a low-side/high-side gate driver implementation for power devices running at high switching frequencies and under very high switching speeds. An electromagnetic interference (EMI) optimization is done by modifying the parasitic capacitance of the propagation paths between the power and the control sides, thanks to a specific design of the circuit. Moreover, to reduce the parasitic inductances and to minimize the antenna phenomenon, the paper studies which elements of the drivers’ circuitry must be brought as close as possible to the power parts. This is important when the ambient temperature of the power device becomes critical, for instance, in automotive and aeronautic applications. Simulations and experiments validate the advantages of the proposed architecture on the conducted EMI problem.

44 citations

Proceedings ArticleDOI
01 Nov 2017
TL;DR: In this article, a general review on the properties of these materials comparing some performance between Si and SiC devices for typical power electronics applications is provided, based on studied information, line of progress and current state of developing, SiC seems to be the most viable substitute in high power and high temperature applications in the mid-term of Si, due to the fact that the GaN is still used in a reduced number of applications.
Abstract: Silicon (Si) power devices have dominated the world of Power Electronics in the last years, and they have proven to be efficient in a wide range of applications. But high power, high frequency and high temperature applications require more than Si can deliver. With the advance of technology, Silicon Carbide (SiC) and Gallium Nitride (GaN) power devices have evolved from immature prototypes in laboratories to a viable alternative to Si-based power devices in high-efficiency and high-power density applications. SiC and GaN devices have several compelling advantages: high-breakdown voltage, high-operating electric field, high-operating temperature, high-switching frequency and low losses. This paper provides a general review on the properties of these materials comparing some performance between Si and SiC devices for typical power electronics applications. Based on studied information, line of progress and the current state of developing, SiC seems to be the most viable substitute in high power and high temperature applications in the mid-term of Si, due to the fact that the GaN is still used in a reduced number of applications.

44 citations

Journal ArticleDOI
TL;DR: The optimization algorithm maximizes the converter efficiency while minimizing the transformer size, and a virtual prototyping tool is developed based on a genetic algorithm with numerical simulations, and in turn, is used to optimize the converter.
Abstract: This article presents the design and optimization of a suitable topology for an isolated dc–dc auxiliary power supply with high isolation voltage and low coupling capacitance. The converter consists of a GaN HEMT inverter operating at 6.78 MHz, an LCC resonance tank, and a class-E low d v /d t rectifier. Furthermore, the galvanic isolation is implemented using a coreless planar transformer that enables higher insulation voltage with similar or better converter efficiency compared to designs using a magnetic material. An analytical design methodology is developed, however, SPICE investigations show that optimal designs might lie outside the validity of the design equations. Consequently, a virtual prototyping tool is developed based on a genetic algorithm with numerical simulations, and in turn, is used to optimize the converter. The optimization algorithm maximizes the converter efficiency while minimizing the transformer size. Prototypes are constructed based on the resulting Pareto front. Experimental results show the validity of the simulated results. Prototypes transferring power up to 15 W with a peak efficiency of 81% are shown. The selected topology enables insulating voltages exceeding 40 kV and coupling capacitances below 10 pF.

32 citations

Journal ArticleDOI
TL;DR: The propagation paths of parasitic currents through the gate driver circuitries, exited under high switching speeds, are studied in different configurations trying to minimize common mode currents generated.
Abstract: This paper presents a study on the gate driver circuitries that need to be implemented to drive several power devices when associated in series connection. More specifically, the propagation paths of parasitic currents through the gate driver circuitries, exited under high switching speeds, are studied in different configurations trying to minimize common mode currents generated. In a gate driver circuitry for a regular low side–high side switching cell configuration with one upper switch and one lower switch, the voltage transient dv/dt at the middle point applied across the primary-secondary parasitic capacitance of gate driver supplies, and control signal isolation units are the reasons for the generation of conducted electromagnetic interference (EMI) perturbations. In complex power converters, multicell, multilevel, or even series connection of power devices, many driver circuits are required and implemented. Similarly, in such converters, there are several dv/dt sources generated at different floating points producing conducted EMI perturbations from the power part to the control part through many gate driver circuitries. Based on previous works, this paper analyzes the best configuration to minimize parasitic currents, especially reducing the conducted common mode currents in series connected transistors topologies. Simulations and practical results validate the analysis for two power devices in series connection, and then the extrapolations for more power devices in series connection, up to six are discussed and analyzed with the help of simulations results.

30 citations

Proceedings ArticleDOI
20 Feb 2018
TL;DR: The main constraints and issues of the SiC-MOSFET switching process are presented, and some recent proposed Gate Drivers to solve these constraints are presented throughout this work.
Abstract: Silicon (Si) power devices have dominated the world of Power Electronics in the last years, and they have proven to be efficient in a wide range of applications. But high power, high frequency and high temperature applications require more than Si can deliver. Wide Band-Gap (WBG) materials such as Silicon Carbide (SiC) and Gallium Nitride (GaN) were intensively researched and developed for power applications due to the substantial advantages their inherent material properties could realize at device level. The SiC-MOSFET has unique capabilities that make it a superior switch when compared to its silicon counterparts. By nature of its material advantages, SiC MOSFETs provide lower switching loss, lower ON-resistance across its operating temperature range, and superior thermal properties. However the characteristics of SiC devices require consideration of the gate-driver circuit to optimize the switching performance. SiC-MOSFETs, due to their ultra fast switching speed, are susceptible to have harsh transients introduced by rapid change in the drain-to-source voltage. Therefore, the gate drive requirements of SiC-MOSFETs require a thorough analysis in order to prevent high dv/dt transients from causing erratic switching behavior or unnecessary switching loss. This paper provides a general review on the properties of SiC comparing some performances between Si-MOSFETs and SiC-MOSFETs for typical power electronics applications. The main constraints and issues of the SiC-MOSFET switching process are presented, and some recent proposed Gate Drivers to solve these constraints are presented throughout this work.

27 citations


Cited by
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Journal ArticleDOI
TL;DR: The literature on EMI research in power electronics systems with WBG devices is reviewed, and the EMI-related reliability issues are discussed, and solutions and guidelines are presented.
Abstract: Wide-bandgap (WBG) power semiconductor devices have become increasingly popular due to their superior characteristics compared to their Si counterparts. However, their fast switching speed and the ability to operate at high frequencies brought new challenges, among which the electromagnetic interference (EMI) is one of the major concerns. Many works investigated the structures of WBG power devices and their switching performance. In some cases, the conductive or radiated EMI was measured. However, the EMI-related topics, including their influence on noise sources, noise propagation paths, EMI reduction techniques, and EMC reliability issues, have not yet been systematically summarized for WBG devices. In this article, the literature on EMI research in power electronics systems with WBG devices is reviewed. Characteristics of WBG devices as EMI noise sources are reviewed. EMI propagation paths, near-field coupling, and radiated EMI are surveyed. EMI reduction techniques are categorized and reviewed. Specifically, the EMI-related reliability issues are discussed, and solutions and guidelines are presented.

153 citations

Journal ArticleDOI
TL;DR: In this article, a gate driver for mediumvoltage (MV) SiC devices is proposed, which has low input common mode current and a short-circuit protection scheme specifically designed for 10-kV SiC mosfet s.
Abstract: Medium-voltage (MV) silicon carbide (SiC) devices have opened up new areas of applications which were previously dominated by silicon-based IGBTs From the perspective of a power converter design, the development of MV SiC devices eliminates the need for series connected architectures, control of multilevel converter topologies which are necessary for MV applications, and the inherent reliability issues associated with it However, when SiC devices are used in these applications, they are exposed to a high peak stress (5–10 kV) and a very high $dv/dt$ (10–100 kV/ $\mu$ s) Using these devices calls for a gate driver with a dc–dc isolation stage that has ultralow coupling capacitance in addition to be able to withstand the high isolation voltage This paper presents a new MV gate driver design to address these issues while maintaining a minimal footprint for the gate driver An MV isolation transformer is designed with a low interwinding capacitance, while maintaining the clearance, creepage, as well as insulation standards A dc isolation test has been performed to validate the integrity of the insulating material The key features include low input common mode current, and a short-circuit protection scheme specifically designed for 10 kV SiC mosfet s The performance of the gate driver is evaluated using double pulse tests and continuous tests Experimental results validate the advantages of the gate driver and its application for MV SiC devices exhibiting very high $dv/dt$ The proposed gate driver concept is aimed at providing an efficient and reliable method to drive MV SiC devices

91 citations