This paper presents the design of a direct-injection divide-by-3 frequency divider operating at the K -band. The divider is implemented in a 0.18- μm CMOS process. The measured free-running frequency of the divider is 7.96 GHz. By utilizing a floating-source differential injector and without a varactor tuning in the divider core, the total locking range is 3.2 GHz with a power consumption of 8.28 mW from a supply voltage of 0.9 V. The total power consumption of the buffers is 9.54 mW from a supply voltage of 1.8 V. The measured phase noise of the divider is -141.3 dBc/Hz at 1-MHz offset when the input referred signal with a phase noise of -132.8 dBc/Hz at 1-MHz offset from 24 GHz. The phase-noise difference of 8.5 dB is close to the theoretical value of 9.5 dB for division-by-3. The output power of the divider is more than -11 dBm over the whole locking range.

Low-Voltage $K$ -Band Divide-by-3 Injection-Locked Frequency Divider With Floating-Source Differential Injector

A self-healing two-stage millimeter-wave broadband power amplifier (PA) with on-chip amplitude/phase compensation is realized in 65-nm CMOS. The amplitude and phase compensations are accomplished by using feedback bias/capacitive schemes to extend the linear operation region and optimize the PA efficiency. Tunable control knobs are inserted in the linearization block to enhance the PA performance yield against process/temperature variations and device ageing effects. This prototype shows a 5.5-dB improvement of the output 1-dB compression point (P1dB) and a less than 2% chip-to-chip gain variation. At a 1-V supply, the differential PA achieves a saturation output power (Psat) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the amplitude compensation, P1dB is increased to 13.7 dBm. With the phase compensation, the output phase variation is decreased to less than 0.5°. To the best of our knowledge, this prototype provides the highest Psat and P1dB with simultaneously high PAE from a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7-GHz 3-dB bandwidth from 55.5 to 62.5 GHz with a compact total area of 0.042 mm2.

Millimeter-Wave Self-Healing Power Amplifier With Adaptive Amplitude and Phase Linearization in 65-nm CMOS

Most of the traditional RF circuits are static or minimally tunable using some digital controllability. For example, high power, low power and shut down modes are available in some commercially available transceivers. If available, the tuning knobs affect different specifications in an interdependent manner, resulting in changing several specifications when only one needs to be tuned. This is not enough for power optimal operation of complete self-aware self-adaptive circuits and systems. Independent or orthogonal tunability of the important conflicting specifications using built-in tuning knobs allow optimal adaptation of the wire-less systems. In this paper we demonstrate the design and benefits of orthogonal tuning knobs using an inductorless LNA as a test vehicle. The design of an orthogonally tunable LNA is discussed that has a 14 dB Gain tuning range and 30 dB OIP3 tuning range as its power consumption goes down by 20×. Measurement results on this LNA validate the concept of orthogonal tunability. Use of this orthogonally tunable LNA within an adaptive wireless receiver framework shows power savings of 2× compared to a static system and an extra savings of 22% compared to a traditional nonorthogonal adaptive system.

A Power-Scalable Channel-Adaptive Wireless Receiver Based on Built-In Orthogonally Tunable LNA

The availability of wide-band low-power frequency dividers is fundamental in transceivers for emerging mm-wave applications. Up to date injection locked topologies have been investigated for very high frequency operations but at the price of large area and limited frequency range. In this work, we investigate a new class based on dynamic latches with load modulation. The proposed latches can be viewed as the evolution of classic static CML latches where the regenerative cross-coupled pair is removed for minimum parasitic at output nodes, i.e., maximum speed, and loads are modulated by the input clock for maximum charge retention during hold times. A time-domain circuit inspection aimed at deriving analytical expressions for maximum and minimum operation frequency and providing guidelines for optimum design is reported. Prototypes of dividers by 4, realized in 32 nm bulk CMOS, operate between 14 GHz and 70 GHz, demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8 mW of maximum power consumption and 55 ×18 μm2 occupied area.

Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation

This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.

A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method

In this paper, a novel design technique of common-gate inductive feedback is presented for millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor at the common-gate transistor of the cascode stage, the gain of the LNA can be enhanced even under a wideband operation. Using a 65nm CMOS process, transmission-line-based and spiral-inductor-based LNAs are fabricated for demonstration. With a dc power consumption of 33.6 mW from a 1.2-V supply voltage, the transmission-line-based LNA exhibits a gain of 20.6 dB and a noise figure of 5.4 dB at 60 GHz while the 3dB bandwidth is 14.1 GHz. As for the spiral-inductor-based LNA, consuming a dc power of 28.8 mW from a 1.2-V supply voltage, the circuit shows a gain of 18.0 dB and a noise figure of 4.5 dB at 60 GHz while the 3dB bandwidth is 12.2 GHz.

60GHz high-gain low-noise amplifiers with a common-gate inductive feedback in 65nm CMOS

A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal.

Cmos millimeter-wave variable-gain low-noise amplifier

A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element.

Low-noise amplifier with gain enhancement

A self-healing two-stage 60 GHz power amplifier (PA) with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region and enhance chip-to-chip performance yield; allowing a 5.5 dB improvement of the output 1-dB compression point (P 1dB ) and a less than 2% chip-to-chip gain variation. At a 1 V supply, the fully differential PA achieves a saturation output power (P sat ) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the on-chip amplitude compensation, the P 1dB is extended to 13.7 dBm. With the on-chip phase compensation, the output phase variation is minimized to less than 0.5 degree. To the best of our knowledge, this PA provides the highest P sat and P 1dB with simultaneous high PAE for a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7 GHz bandwidth from 55.5 to 62.5 GHz with a very compact area of 0.042 mm2.

A V-band self-healing power amplifier with adaptive feedback bias control in 65 nm CMOS

In this paper, a novel circuit topology of CMOS divide-by-three injection-locked frequency divider is demonstrated. By using a differential direct injection pair with a LC-tank oscillator, the proposed circuit can perform the division ratio of three while the wide locking range is obtained. Based on the presented circuit architecture, a V-band frequency divider is implemented in 65-nm CMOS for demonstration. Operated at a supply voltage of 1.0 V, the divider core consumes a dc power of 5.2 mW. At an incident power of 0 dBm, the fabricated circuit exhibits an input locking range from 58.6 to 67.2 GHz. The measured output power and locked phase noise at a 1-MHz offset are −10 dBm and −127 dBc/Hz, respectively. To the authors' best knowledge, this work is the first CMOS V-band divide-by-three injection-locked frequency divider owning a locking range over 10% without any tuning mechanism reported to date.

Po-Yi Wu

Papers

60GHz high-gain low-noise amplifiers with a common-gate inductive feedback in 65nm CMOS

Cmos millimeter-wave variable-gain low-noise amplifier

Low-noise amplifier with gain enhancement

A V-band self-healing power amplifier with adaptive feedback bias control in 65 nm CMOS

A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS