Pong-Fei Lu

Bio: Pong-Fei Lu is an academic researcher from IBM. The author has contributed to research in topics: Bipolar junction transistor & Transistor. The author has an hindex of 22, co-authored 65 publications receiving 1386 citations.

Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories

Abstract: A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

Physical design of a fourth-generation POWER GHz microprocessor

Abstract: The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V.

Collector-base junction avalanche effects in advanced double-poly self-aligned bipolar transistors

Abstract: Observation of base-current reversal induced by avalanche multiplication is reported in advanced self-aligned bipolar devices at a collector junction reverse bias less than 3 V. Temperature measurements were carried out to verify the avalanche mechanism, and the dependence on the collector doping profile and high-level injection effects was investigated both experimentally and by numerical simulations. The avalanche effect, which is expected to aggravate with scaling, will eventually threaten normal circuit operation if certain criteria for base-collector reverse bias cannot be maintained. >

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference

Abstract: A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers. With a programmable architecture and custom ISA, this engine achieves >90% sustained utilization across the range of neural network topologies by employing a dataflow architecture and an on-chip scratchpad hierarchy. Compute precision is optimized at 16b floating point (fp 16) for high model accuracy in training and inference as well as 1b/2b (bi-nary/ternary) integer for aggressive inference performance. At 1.5 GHz, the AI core prototype achieves 1.5 TFLOPS fp 16, 12 TOPS ternary, or 24 TOPS binary peak performance in 14nm CMOS.

Floating-body effects in partially depleted SOI CMOS circuits

Abstract: This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

Fundamentals of Modern VLSI Devices

Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

Introduction to the cell multiprocessor

Abstract: This paper provides an introductory overview of the Cell multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discusses the history of the project, the program objectives and challenges, the disign concept, the architecture and programming models, and the implementation.

A new recombination model for device simulation including tunneling

Abstract: A recombination model for device simulation that includes both trap-assisted tunneling (under forward and reverse bias) and band-to-band tunneling (Zener tunneling) is presented. The model is formulated in terms of analytical functions of local variables, which makes it easy to implement in a numerical device simulator. The trap-assisted tunneling effect is described by an expression that for weak electric fields reduces to the conventional Shockley-Read-Hall (SRH) expression for recombination via traps. Compared to the conventional SRH expression, the model has one extra physical parameter, the effective mass m*. For m*=0.25 m/sub 0/ the model correctly describes the experimental observations associated with tunneling. The band-to-band tunneling contribution is found to be important at room temperature for electric fields larger than 7*10/sup 5/ V/cm. For dopant concentrations above 5*10/sup 17/ cm/sup -3/ or, equivalently, for breakdown voltages below approximately 5 V, the reverse characteristics are dominated by band-to-band tunneling. >

ESD in silicon integrated circuits

Abstract: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications

Abstract: The silicon-germanium heterojunction bipolar transistor (SiGe HBT) is the first practical bandgap-engineered device to be realized in silicon. SiGe HBT technology combines transistor performance competitive with III-V technologies with the processing maturity, integration levels, yield, and hence, cost commonly associated with conventional Si fabrication. In the ten-and-one-half years since the first demonstration of a functional transistor, SiGe HBT technology has emerged from the research laboratory, entered manufacturing on 200-mm wafers, and is poised to enter the commercial RF and microwave market. State-of-the-art SiGe HBT's can deliver: (1) f/sub T/ in excess of 50 GHz; (2) f/sub max/ in excess of 70 GHz; (3) minimum noise figure below 0.7 dB at 2.0 GHz; (4) 1/f noise corner frequencies below 500 Hz; (5) cryogenic operation; (6) excellent radiation hardness; (7) competitive power amplifiers; and (8) reliability comparable to Si. A host of record-setting digital, analog, RF, and microwave circuits have been demonstrated in the past several years using SiGe HBT's, and recent work on passives and transmission lines on Si suggest a migratory path to Si-based monolithic microwave integrated circuits (MMIC's) is possible. The combination of SiGe HBT's with advanced Si CMOS to form an SiGe BiCMOS technology represents a unique opportunity for Si-based RF system-on-a-chip solutions. This paper reviews state-of-the-art SiGe HBT technology and assesses its potential for current and future RF and microwave systems.