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Author

Pooja R. Batra

Bio: Pooja R. Batra is an academic researcher from IBM. The author has contributed to research in topics: Dram & Chip. The author has an hindex of 6, co-authored 9 publications receiving 75 citations.
Topics: Dram, Chip, eDRAM, Wafer bonding, Integrated circuit

Papers
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Journal ArticleDOI
TL;DR: In this paper, the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery.
Abstract: For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation.

19 citations

Proceedings ArticleDOI
01 Oct 2013
TL;DR: In this article, the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata.
Abstract: For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch <;= 5μ range using available tooling. Prior work [3] has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core [4] requiring neither re-design nor modification of the existing CMOS fabrication process. Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 1.48GHz 3D stacked EDRAM operation.

14 citations

Journal ArticleDOI
TL;DR: 3D DRAMs including DDR3, wide I/O mobile DRAM, and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems are reviewed.
Abstract: This paper describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs). We review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems. We then cover embedded 3D DRAM for high-performance cache memories, reviewing an early cache prototype employing face-to-face 3D stacking which confirmed negligible performance and retention degradation using 32 nm server and ASIC embedded DRAM macros. A second cache system prototype based on POWER7 was developed to confirm feasibility of stacking $\mu {\rm P}$ and high density cache memory, with $> 2~{\rm GHz}$ operation. For test and assembly, a micro-electro-mechanical-system (MEMS) probe-card with an integrated active silicon chip, realized a 50 $\mu{\rm m}$ pitch micro-probing at-speed-active-test for known-good-die (KGD) sorting. Finally, oxide wafer bonding with Cu TSV demonstrated wafer-scale 3D integration, with TSV diameters as small as 1 $\mu{\rm m}$ . The paper concludes with comments on the challenges for future 3D DRAMs.

14 citations

Proceedings ArticleDOI
01 Oct 2014
TL;DR: In this article, a proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects is reported.
Abstract: Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

11 citations

Patent
24 Aug 2015
TL;DR: In this article, a double-sided three-dimensional (3D) hierarchal architecture for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring is presented.
Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.

11 citations


Cited by
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Patent
27 Mar 2017
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Abstract: An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

185 citations

Journal ArticleDOI
TL;DR: The latest progress in the area of micro/nanoscale 3D assembly, covering the various classes of methods through rolling, folding, curving, and buckling assembly, is discussed, focusing on the design concepts, principles, and applications of different methods, followed by an outlook on the remaining challenges and open opportunities.
Abstract: The miniaturization of electronics has been an important topic of study for several decades. The established roadmaps following Moore's Law have encountered bottlenecks in recent years, as planar processing techniques are already close to their physical limits. To bypass some of the intrinsic challenges of planar technologies, more and more efforts have been devoted to the development of 3D electronics, through either direct 3D fabrication or indirect 3D assembly. Recent research efforts into direct 3D fabrication have focused on the development of 3D transistor technologies and 3D heterogeneous integration schemes, but these technologies are typically constrained by the accessible range of sophisticated 3D geometries and the complexity of the fabrication processes. As an alternative route, 3D assembly methods make full use of mature planar technologies to form predefined 2D precursor structures in the desired materials and sizes, which are then transformed into targeted 3D mesostructures by mechanical deformation. The latest progress in the area of micro/nanoscale 3D assembly, covering the various classes of methods through rolling, folding, curving, and buckling assembly, is discussed, focusing on the design concepts, principles, and applications of different methods, followed by an outlook on the remaining challenges and open opportunities.

94 citations

Book ChapterDOI
17 Aug 2016
TL;DR: This paper is the first to enable the run-time access of decay-based intrinsic DRAM PUFs in commercial off-the-shelf systems, which requires no additional hardware or FPGA implementations for their operation.
Abstract: A Physically Unclonable Function (PUF) is a unique and stable physical characteristic of a piece of hardware, which emerges due to variations in the fabrication processes. Prior works have demonstrated that PUFs are a promising cryptographic primitive to enable secure key storage, hardware-based device authentication and identification. So far, most PUF constructions require addition of new hardware or FPGA implementations for their operation. Recently, intrinsic PUFs, which can be found in commodity devices, have been investigated. Unfortunately, most of them suffer from the drawback that they can only be accessed at boot time. This paper is the first to enable the run-time access of decay-based intrinsic DRAM PUFs in commercial off-the-shelf systems, which requires no additional hardware or FPGAs. A key advantage of our PUF construction is that it can be queried during run-time of a Linux system. Furthermore, by exploiting different decay times of individual DRAM cells, the challenge-response space is increased. Finally, we introduce lightweight protocols for device authentication and secure channel establishment, that leverage the DRAM PUFs at run-time.

62 citations

Journal ArticleDOI
TL;DR: Technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps are reviewed and future outlook on the potential growth of research in this area is discussed.

57 citations

Journal ArticleDOI
Subramanian S. Iyer1
TL;DR: The key attributes of 3D integration, the enablers and the challenges that need to be overcome before widespread acceptance by industry are developed.
Abstract: The field of electronics packaging is undergoing a significant transition to accommodate the slowing down of lithographically driven semiconductor scaling. Three-dimensional (3D) integration is an important component of this transition and promises to revolutionize the way chips are assembled and interconnected in a subsystem. In this article, we develop the key attributes of 3D integration, the enablers and the challenges that need to be overcome before widespread acceptance by industry. While we are already seeing the proliferation of applications in the memory subsystem, the best is yet to come with the heterogeneous integration of a diverse set of technologies, the mixing of lithographic nodes and an economic argument for its implementation based on overall system function, and cost rather than a narrow component-based analysis. Finally, an extension to monolithic 3D integration promises even further benefits.

53 citations