There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

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Design Of Analog Cmos Integrated Circuits

This chapter contains sections titled: Introduction Overview of Multicarrier CDMA Systems Channel Model Performance of MC-CDMA System Performance of Overlapping Multicarrier DS-CDMA Systems Performance of Multicarrier DS-CDMA-I Systems Performance of AMC DS-CDMA Systems Performance of SFH/MC DS-CDMA Systems Chapter Summary and Conclusion 
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Overview of Multicarrier CDMA

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

A detailed presentation of the latest version of the Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of low-doped ultrathin body and buried oxide fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this part, a full analytical calculation of interface potentials, valid for all regimes of independent double-gate device operation, is detailed. This analytical computation, which is the heart of Leti-UTSOI2, provides explicit expressions for all quantities required to build dc and ac core models.

Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part I: Interface Potentials Analytical Model

Multi-carrier code division multiple access (MCCDMA) is an attractive choice for high speed wireless communication as it mitigates the problem of inter symbol interference (ISI) and also exploits frequency diversity. In orderto support multiple users with high speed data communications, the MC-CDMA technique is used to address these challenges. In this paper working of Transmitter and Receiver model of MCCDMA system is presented. This work also derives simulation through MATLAB of average bit error rate (BER) versus bit energy to noise ratio (Eh/No) of Multi Carrier Code Division Multiple Access (MC-CDMA) systems using various detection techniques which are used for both uplink & downlink MCCDMA systems i.e. Maximal Ratio Combining (MRC) and Equal Gain Combining (EGC) with synchronization errors over Rayleigh channel using BPSK modulation and Additive White Gaussian Noise, which shows the reduction in BER performance.

Muti-Carrier CDMA overview with BPSK modulation in Rayleigh channel

In this paper, we present a generic surface potential based current voltage ( I – V ) model for doped or undoped asymmetric double gate (DG) MOSFET. The model is derived from the 1-D Poisson’s equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton–Raphson iterative method. A noncharge sheet based drain current model based on the Pao-Sah’s double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potential and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.

A surface potential based drain current model for asymmetric double gate MOSFETs

https://onlinelibrary.wiley.com/doi/pdf/10.1002/eng2.12086

Impact of high mobility III‐V compound material of a short channel thin‐film SiGe double gate junctionless MOSFET as a source

This paper presents a systematic analytical model development for a sub-45-nm gate length double gate tunnel FET (DG TFET) and assessment of the tunneling current based on classical model under asymmetric circumstances with the ambipolar characteristic. Performance analysis of the tunneling current for a sub-45-nm gate length TFET is performed using Kane’s model by considering high doping in the source and drain regions keeping the channel region low doped. The model explains the variation of tunneling current with the change in oxide thickness under symmetric front and back gate voltages with 5 eV metal work function. The variation in tunnel current is also analyzed for the change in channel thickness under symmetric front and back gate voltages for symmetric oxide thickness. The increase in tunneling current for channel thickness scaling under asymmetric operation of the DG TFET is also efficiently captured by the developed model. The model is compared and verified with Sentaurus TCAD for all bias conditions and good agreement has been achieved.

Pradipta Dutta

Papers

Muti-Carrier CDMA overview with BPSK modulation in Rayleigh channel

A surface potential based drain current model for asymmetric double gate MOSFETs

Impact of high mobility III‐V compound material of a short channel thin‐film SiGe double gate junctionless MOSFET as a source

An Analytical BTBT Current Model of Symmetric/Asymmetric 4T Tunnel Double Gate FETs With Ambipolar Characteristic

Performance Analysis of Gate Stack DG-MOSFET for Biosensor Applications