Prakash R. Apte

Bio: Prakash R. Apte is an academic researcher from Indian Institute of Technology Bombay. The author has contributed to research in topics: Taguchi methods & Threshold voltage. The author has an hindex of 7, co-authored 48 publications receiving 166 citations. Previous affiliations of Prakash R. Apte include Indian Institutes of Technology & Datta Meghe College of Engineering.

Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage

Abstract: This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time Taguchi method determines the setting of process parameters in experimental design while analysis of variance (ANOVA) determines the influence of the main process parameters on threshold voltage The fabrication processes of the transistor were performed by ATHENA fabrication simulator, while the electrical characterization of the device was done by an ATLAS characterization simulator These two simulators were combined and the results were analyzed by Taguchi’s method in order to aid in design and optimizing process parameters Threshold voltage (Vth) results were used as the evaluation parameters The results show that the VTH value of –010319 V is achieved for a 32 nm PMOS transistor In conclusion, by utilizing Taguchi’s method to analyze the effect of process parameters, we can adjust threshold voltage (VTH) for PMOS to a stable value of –010319 V that is wellwithin ITRS prediction for a 32 nm PMOS transistor Key words: 32 nm PMOS device, HALO, compensation implantation, S/D implantation,threshold voltage, Taguchi’s method

A new input-output based model coverage paradigm for control blocks

Abstract: Safety critical control systems, especially flight control systems, have failed in trials and actual flights sometimes killing people. Independence is a key word in the verification and validation activity of such systems. Model based testing is used today in all flight control programs. Test cases are generated using qualified automated tools or manually to ensure code and requirements coverage. A new paradigm of coverage metric is developed here for the independent verification. This has been developed for control systems represented as Simulink blocks. The coverage metrics are defined as pairs of cells. One cell has a True/False discrete metric, which indicates if a particular functionality has been covered. The other cell has the continuous metric, which indicates a distance to nominal, or coverage. The efficacy of these metrics is determined by tests using mutant code. Matlab code corresponding to the model is mutated to generate several mutant files. It is shown that the test cases developed using this coverage metric bring out the errors introduced in the mutant files. It was possible to use these metrics to optimize test cases successfully using the Taguchi Design of Experiments methodology. 1 2

Optimization of process parameter variation in 45nm p-channel MOSFET using L 18 orthogonal array

Abstract: In this study, orthogonal array of L 18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH ) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the PMOS device. There are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of V TH for every row of experiment. V TH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with L 18 Orthogonal Array to aid in design and optimize the process parameters. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In PMOS device, V TH implant dose (26%) and compensate implant dose (26%) were the major factors affecting the threshold voltage. While S/D Implant was identified as an adjustment factor in PMOS device. These adjustment factors have been used to get the nominal values of threshold voltage for PMOS device closer to −0.289V.

A novel EBG structure with super-wideband suppression of simultaneous switching noise in high speed circuits

Abstract: A novel uniplanar electromagnetic band-gap structure to maintain power integrity by suppressing simultaneous switching noise (SSN) is presented. The EBG structure with stopband from 750 MHz to 5.10 GHz is designed, fabricated and validated using network analyzer. Simulation results are verified by measurements and compared with the earlier published structures. Suppression of resonant cavity modes of power plane by EBG structure is also shown. The adoption of EBG structure in power deliver network is recommended to reduce the high frequency noise coupling between neighboring devices. These structures further help in better EMI/EMC compliance of the product by attenuating the propagation of high frequency noise between devices. The EBG structure usage can be on board, package or at die level.

Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization

Abstract: Power Integrity problem for a high speed power plane is discussed in context of selection and placement of decoupling capacitors. The s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their optimum locations on the board are found using particle swarm optimization. A novel and accurate methodology is presented which can be used for any high speed Power delivery Network.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Myth Busters: Dietary Supplements and COVID-19.

Abstract: News and social media platforms have implicated dietary supplements in the treatment and prevention of coronavirus disease 2019 (COVID-19). During this pandemic when information quickly evolves in the presence of contradicting messages and misinformation, the role of the pharmacist is essential. Here, we review theoretical mechanisms and evidence related to efficacy and safety of select supplements in the setting of COVID-19, including vitamin C, vitamin D, zinc, elderberry, and silver. Evidence evaluating these supplements in COVID-19 patients is lacking, and providers and patients should not rely on dietary supplements to prevent or treat COVID-19. Rather, reference to evidence-based guidelines should guide treatment decisions.

Compensation of the Current-Transformer Saturation Effects for Digital Relays

Abstract: A current transformer (CT) is accurately modeled for representation of the CT saturation effects on digital protective relays. Simulation studies performed in the PSCAD/EMTDC platform are used to investigate the impacts of CT saturation on the current phasor estimation. A new algorithm is also proposed for detection and compensation of CT saturation effects, based on: a least error squares (LES) filter which estimates the phasor parameters of the CT secondary current; a novel saturation detection method which uses the output of the LES filter for saturation detection; and a new minimum estimation error tracking approach which enhances the precision of the phasor estimation. The proposed saturation detection/compensation algorithm is independent of the parameters of the CT, the burden, and the power system. The study results show that the proposed algorithm: 1) reconstructs the distorted current waveform, under dc and ac saturation conditions, with the required precision and speed and 2) performs satisfactorily under inductive burden and under deep and slight saturation conditions.

Harnessing voltage margins for energy efficiency in multicore CPUs

Abstract: In this paper, we present the first automated system-level analysis of multicore CPUs based on ARMv8 64-bit architecture (8-core, 28nm X-Gene 2 micro-server by AppliedMicro) when pushed to operate in scaled voltage conditions. We report detailed system-level effects including SDCs, corrected/uncorrected errors and application/system crashes. Our study reveals large voltage margins (that can be harnessed for energy savings) and also large $V_{min}$ variation among the 8 cores of the CPU chip, among 3 different chips (a nominal rated and two sigma chips), and among different benchmarks.Apart from the $V_{min}$ analysis we propose a new composite metric (severity) that aggregates the behavior of cores when undervolted and can support system operation and design protection decisions. Our undervolting characterization findings are the first reported analysis for an enterprise class 64-bit ARMv8 platform and we highlight key differences with previous studies on x86 platforms. We utilize the results of the system characterization along with performance counters information to measure the accuracy of prediction models for the behavior of benchmarks running in particular cores. Finally, we discuss how the detailed characterization and the prediction results can be effectively used to support design and system software decisions to harness voltage margins for energy efficiency while preserving operation correctness. Our findings show that, on average, 19.4% energy saving can be achieved without compromising the performance, while with 25% performance reduction, the energy saving raises to 38.8%.CCS CONCEPTS• Hardware → Power and energy → Power estimation and optimization; • Hardware → Robustness → Hardware reliability → Process, voltage and temperature variations

Chemical Modifications of Cassava Peel as Adsorbent Material for Metals Ions from Wastewater

Abstract: Residues from the processing of cassava roots (Manihot esculenta Crantz), or cassava peels, are evaluated as chemically modified adsorbents with H2O2, H2SO4, and NaOH, in the removal of metal ions Cd(II), Pb(II), and Cr(III) from contaminated water. Modified adsorbents were chemically characterized for their chemical composition and (point of zero charge), while adsorption tests determined the best conditions of pH, adsorbent mass, and contact time between adsorbent and adsorbate in the process of removal of the metal ions. Isotherms obtained from the preliminary results were linearized by Langmuir’s and Freudlich’s models. The thermodynamic parameters, such as , , and , were also evaluated. The modifying solutions proposed were effective in the modification of adsorbents and resulted in high capacity sorption materials. Equilibrium time between adsorbent and adsorbate for the solutions contaminated with metals is about 40 minutes. The Langmuir model adjusted to most results, indicating monolayers adsorption of Cd(II), Pb(II), and Cr(III). The values obtained for Langmuir show a higher adsorption capacity caused by chemical modifications, with values such as 19.54 mg Cd(II) per g of M. NaOH, 42.46 mg of Pb(II) per g of M. NaOH, and 43.97 mg of Cr(III) per g of M H2O2. Results showed that modified cassava peels are excellent adsorbent, renewable, high availability, and low-cost materials and a feasible alternative in the removal of metals in industries.