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Prasad Joshi
Researcher at Intel
Publications - 5
Citations - 2612
Prasad Joshi is an academic researcher from Intel. The author has contributed to research in topics: Spiking neural network & Neuromorphic engineering. The author has an hindex of 5, co-authored 5 publications receiving 1355 citations. Previous affiliations of Prasad Joshi include University of Southern California.
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Journal ArticleDOI
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning
Michael Davies,Narayan Srinivasa,Tsung-Han Lin,Gautham N. Chinya,Cao Yongqiang,Sri Harsha Choday,Georgios D. Dimou,Prasad Joshi,Nabil Imam,Shweta Jain,Yuyun Liao,Chit-Kwan Lin,Andrew Lines,Ruokun Liu,Deepak A. Mathaikutty,Steven McCoy,Arnab Paul,Jonathan Tse,Guruguhanathan Venkataramanan,Yi-Hsin Weng,Andreas Wild,Yoon Seok Yang,Hong Wang +22 more
TL;DR: Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon, and can solve LASSO optimization problems with over three orders of magnitude superior energy-delay-product compared to conventional solvers running on a CPU iso-process/voltage/area.
Journal ArticleDOI
Advancing Neuromorphic Computing With Loihi: A Survey of Results and Outlook
Michael Davies,Andreas Wild,Garrick Orchard,Yulia Sandamirskaya,Gabriel A. Fonseca Guerra,Prasad Joshi,Philipp Plank,Sumedh R. Risbud +7 more
TL;DR: Loihi as mentioned in this paper is a neuromorphic research processor designed to support a broad range of spiking neural networks with sufficient scale, performance, and features to deliver competitive results compared to state-of-the-art contemporary computing architectures.
Proceedings ArticleDOI
Loihi Asynchronous Neuromorphic Research Chip
TL;DR: The pre-silicon design was verified by static timing analysis, back-annotated gate-level simulation, and FPGA emulation, and Tunable delay lines provide sufficient timing margin in extreme corners such as near-threshold-voltage.
Book ChapterDOI
Timing verification of gasp asynchronous circuits: predicted delay variations observed by experiment
TL;DR: In this paper, the authors present spreadsheet calculations intended to verify the timing of 6-4 GasP asynchronous NoC control circuits using the Logical Effort model used to estimate the delays of each logic gate in the GasP control.