A 9 bit 11 GS/s DAC is presented that achieves an SFDR of more than 50 dB across Nyquist and IM3 below 50 dBc across Nyquist. The DAC uses a two-times interleaved architecture to suppress spurs that typically limit DAC performance. Despite requiring two current-steering DACs for the interleaved architecture, the relative low demands on performance of these sub-DACs imply that they can be implemented in an area and power efficient way. Together with a quad-switching architecture to decrease demands on the power supply and bias generation and employing the multiplexer switches in triode, the total core area is only 0.04 mm2 while consuming 110 mW from a single 1.0 V supply.

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An Interleaved Full Nyquist High-Speed DAC Technique

The recently emerging resistive random-access memory (RRAM) can provide nonvolatile memory storage but also intrinsic computing for matrix-vector multiplication, which is ideal for the low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM crossbar--based computing is mainly assumed as a multilevel analog computing, whose result is sensitive to process nonuniformity as well as additional overhead from AD-conversion and I/O. In this article, we explore the matrix-vector multiplication accelerator on a binary RRAM crossbar with adaptive 1-bit-comparator--based parallel conversion. Moreover, a distributed in-memory computing architecture is also developed with the according control protocol. Both memory array and logic accelerator are implemented on the binary RRAM crossbar, where the logic-memory pair can be distributed with the control bus protocol. Experimental results have shown that compared to the analog RRAM crossbar, the proposed binary RRAM crossbar can achieve significant area savings with better calculation accuracy. Moreover, significant speedup can be achieved for matrix-vector multiplication in neural network--based machine learning such that the overall training and testing time can be both reduced. In addition, large energy savings can be also achieved when compared to the traditional CMOS-based out-of-memory computing architecture.

Distributed In-Memory Computing on Binary RRAM Crossbar

The race on the Complementary Metal-Oxide-Semiconductor (CMOS) More Moore integration scale has brought to light several major limitations for efficient planar process integration starting with the 40 nm technology node. The transistor channel was more and more difficult to control in terms of electrostatics, and many process engineering methods (such as, for example, Silicon strain) were used to provide transistors with good carrier speed and decent electrical characteristics. Starting from the 28-nm node, the obvious solution for transistors with increased electrical performances was the use of fully depleted devices. Two integration methods have been identified by the semiconductor industry for these fully depleted devices: Fully Depleted Silicon on Insulator (FD-SOI) CMOS and Fin-FET CMOS devices. While the fundamental carrier semiconductor equations are similar, the process integration is very different. This article focuses on planar FDSOI CMOS technology features as integrated by STMicroelectronics in the 28-nm node [1], [2], and its specificities for analog, radio frequency (RF), millimeter wave (mmW), and mixed signal systemon-chip (SoC) integration.

Fully Depleted Silicon on Insulator Devices CMOS: The 28-nm Node Is the Perfect Technology for Analog, RF, mmW, and Mixed-Signal System-on-Chip Integration

To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is that these ADCs are large and therefore suffer from interleaving artifacts related to size [1]. Compact, efficient SAR ADCs are needed to address this problem. As an alternative, multiple-bit-per-cycle SAR ADCs deliver high speed from a single SAR ADC, but at the cost of significant added complexity (i.e., extra quantizers and capacitor DACs) and die area [2,3]. This work addresses the need for a fast, compact SAR ADC, with a 1GS/s SAR ADC that has the best Walden FOM and the smallest area among 5-to-6.3b ADCs published in ISSCC (see Fig. 27.3.1).

27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC

To sustain ever-growing data traffic, modern wireline communication devices (over copper or fiber optic media) require a high-speed ADC in their receive path to do the digital equalization, or to recover the complex-modulated information A 6b 10GS/s ADC able to acquire up to 20GHz input signal frequency and showing 53 ENOB in Nyquist condition is presented It is based on a Master Track & Hold (T&H) followed by a time-interleaved synchronous SAR ADC, thus avoiding the need for any kind of skew or bandwidth calibration Ultra Thin Body and BOX Fully Depleted SOI (UTBB FDSOI) 28nm CMOS technology is used for its fast switching and regenerating capability The core ADC consumes 32mW from 1V power supply and occupies 0009mm2 area The FoM is 81fJ/conversion step

22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology

A 9b 3GS/s pure binary current steering DAC is implemented in 65nm CMOS. It demonstrates a low noise CML latch and a low power delay balancing technique while drawing 50mA from a single 1.2V power supply. When sampling at 3GHz, it exhibits more than 50dB SFDR until 1.5GHz output frequency and less than −60dB IM3 up to 1GHz output frequency. Total silicon area is less than 0.04mm2.

A 3GS/s, 9b, 1.2V single supply, pure binary DAC with >50dB SFDR up to 1.5GHz in 65nm CMOS

This paper describes a novel low power 10-bit 125 Msps pipelined ADC implemented in 65 nm standard digital CMOS process. Proposed ADC implements 2.5 b/stage with amplifier shared between consecutive stages, achieves best in class FOM of 0.27 pJ/step with conversion power of 0.16 mW/Msps. The ADC amplifier employs novel techniques of adaptive biasing and cross coupled compensation to achieve improved settling behavior with significant power efficiency. This ADC occupies 0.13mm area and achieves maximum 0.3 LSB DNL and 0.6 LSB INL along with 9.26 ENOB at 125 Msps dissipating 20 mW power from 1.2v supply.

20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process

An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

Adaptive delay based asynchronous successive approximation analog-to-digital converter

Estimation of jitter in early design cycle of an SoC is necessary to avoid jitter budget conflicts in the design. In this paper, an analysis of power supply induced jitter in a commonly used voltage mode driver architecture in serial links is discussed. The circuit used for the analysis is designed in 28nm FD-SOI technology but the analysis is technology independent. Jitter induced by noise in power delivery networks is analyzed by a transfer function from power supply to the output by a small signal equivalent model. The analysis can be extended generically for System-On-Chip (SoC) level design considerations.

Pratap Narayan Singh

Papers

22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology

A 3GS/s, 9b, 1.2V single supply, pure binary DAC with >50dB SFDR up to 1.5GHz in 65nm CMOS

20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process

Adaptive delay based asynchronous successive approximation analog-to-digital converter

An analysis of power supply induced jitter for a voltage mode driver in high speed serial links