Prathamesh Chodankar

Bio: Prathamesh Chodankar is an academic researcher from VIT University. The author has contributed to research in topics: Logic gate & Transistor. The author has an hindex of 1, co-authored 1 publications receiving 3 citations.

Low power SRAM design using independent gate FinFET at 30nm technology

Abstract: Energy efficient and low power circuit designing has become challenging for many years Now a day in Modern 1C designing, SRAM design somewhat significant because it will occupy more space on a die and consumes large fraction of energy of the chip Scaling of conventional CMOS circuit leads to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage power increases in the transistor In this paper, to minimize short channel effects, we have designed SRAM cell using double gate FinFET FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily Simulation is performed with Cadence virtuoso tool The low power in SRAM is achieved by driving the two gates of FinFET independently We have designed some SRAM circuits using FinFET and compared their results After that, using the best configuration we have designed 8×8 memory array

Low-power and high-speed 13T SRAM cell using FinFETs

Abstract: Fin field-effect transistors (FinFETs) are replacing the traditional planar metal-oxide-semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

Design of a ternary FinFET SRAM cell

Abstract: The Scaling of conventional CMOSs (Complementary Metal Oxide Semiconductors) has been facing problems such as short channel effect due to hot electron effect and leakage power. To solve the problems, FinFETs (Fin Field Effect Transistor) device structures are solution. Binary System occupies large area there for the circuit complexity is increasing on a VLSI chip and thus, degrading the performance of binary system. MVL (Multi valued logic) is considered as solution to this issue. In this paper, to minimize short channel effect and reduce circuit complexity on a VLSI chip, we have designed ternary Static Random Access Memory (SRAM) Cell using Shorted Gate FinFET (SG-FinFET). FinFET is double gate transistor architecture to extend scaling over planar device. Two gates have better control over the short channel effects. The paper presents a novel design of 6 Transistor ternary SRAM cell, with separate read and write lines. The proposed SRAM cell designed using Tanner tool version 13 and simulated with the help of W-Edit version 13.

Design of Multi-Segment Hybrid Type Content Addressable Memory in High Performance FinFET Technology

Abstract: Power dissipation due to memories has become a major concern of modern digital design. Scaling of CMOS technology has lead to short channel effects. Here CAM cells are designed using FinFET which have better gate control over drain to source current. The CAM cells designed with 30nm LG are used in multi-segment hybrid CAM architecture. The results are compared with the original hybrid CAM. It is observed that the energy metric of proposed architecture is 7% less compared to hybrid CAM.