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Praveen Tripathi

Bio: Praveen Tripathi is an academic researcher from Uttarakhand Technical University. The author has contributed to research in topics: Hyperspectral imaging & VHDL. The author has an hindex of 2, co-authored 2 publications receiving 11 citations.

Papers
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Journal ArticleDOI
TL;DR: The researchers have used High Speed Transceiver Logic for the purpose of energy efficient counter design on Spartan3 (90nm) FPGA using VHDL (VHSIC Hardware Description Language) hardware description language and the Xilinx ISE simulator for the analysis and synthesis of counters.
Abstract: Extending battery life and increase in portability of modern electronic devices and gadgets are the main motives behind the Green Computing which is also known by similar terms like energy efficient design or low power design or green design. Such efficiency is only possible if all the components of processor are also energy efficient. In this work, the researchers tried to analyze the energy optimization possibility in counter design by selection of energy efficient IO standards. The researchers had used High Speed Transceiver Logic for the purpose of energy efficient counter design on Spartan3 (90nm) FPGA (field-programmable gate array) using VHDL (VHSIC Hardware Description Language) hardware description language along with the Xilinx ISE simulator for the analysis and synthesis of counters. Spartan 3 with 90 nm low power is used to achieve substantial power savings. Here, researchers have used five different HSTL IO standards for this work. The standards used are HSTL_I, HSTL_III, HSTL_III_18, HSTL_III_DCI and HSTL_II_18. With these sets of IO standards, Researchers had run their counter design on various device operating frequencies (1.0 GHz to 4.0 GHz). The results clearly indicate that this dynamic frequency (1.0 GHz in lieu of 4.0 GHz) scaling had saved 45% of total power.

9 citations

Journal ArticleDOI
TL;DR: In this article, a relative performance investigation of few commonly used feature extraction techniques like Decision Boundary Feature Extraction (DBFE), Non-Parametric Weighted Feature Extractor (NWFE), Discriminative analysis feature extraction (DAFE) and Principal Component Analysis (PCA) is presented.
Abstract: Obtaining thematic maps using image classification techniques from hyperspectral datasets is a very difficult image processing task. In hyperspectral image analysis dimensionality reduction is one of the challenging pre-processing tasks, which is achieved using feature extraction techniques. The beauty of these techniques is that they drastically reduces the dimensionality of image and at the same time preserves the majority of the essential information. In this paper few most frequently used dimensionality reduction methods are being investigated, which helps to get accurateness. This research work presents a relative performance investigation of few mostly frequently used feature extraction techniques like Decision Boundary Feature Extraction (DBFE), Non-Parametric Weighted Feature Extraction (NWFE), Discriminative analysis feature extraction (DAFE) and Principal Component Analysis (PCA). The classification is carried out using two most widely used classification techniques including Gaussian Maximum Likelihood (GML) and neural network (NNs). The results obtained after performing experiments indicates that Decision Boundary Feature Extraction (DBFE) technique has provided the best accuracy among various investigated feature extraction techniques. The application areas of this research include areas like identification of exact location in battle field, drought affected areas, flooded areas and weather forecasting etc.

4 citations


Cited by
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Book ChapterDOI
06 Dec 2018
TL;DR: This work adopted structure-preserving recursive filter to noise removal and Probabilistic based principal component analysis is applied to reduce dimensionality and obtained results show that the proposed HSI Classification method provides results on par with similar type of methods from literature.
Abstract: Hyper spectral image (HSI) Classification has become important research areas of remote sensing which can be used in many practical applications, including precision agriculture, Land cover mapping, environmental monitoring etc. HSI Classification includes various steps like Noise removal, dimensionality reduction, and classification. In this work, we adopted structure-preserving recursive filter (SPRF) to noise removal and Probabilistic based principal component analysis (PPCA) is applied to reduce dimensionality. Finally classification is performed using multi class large marginal distribution machine (LDM). The proposed (HSI) Classification method is carried out and results are validated across the three widely used standard datasets like Indian Pines, University of Pavia and Salinas. The obtained results show that the proposed method provides results on par with similar type of methods from literature.

19 citations

Journal ArticleDOI
TL;DR: Along with IOs power and total on-chip power, the model has also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.
Abstract: FIR Filter always remains in linear phase with the help of symmetric coefficient. This feature makes it ideal for phase-sensitive applications like data communications. Design of FIR filter with energy efficiency makes excellent sense to achieve energy efficiency in digital selected frequency module of communication. We are using scaling of output load from 5000 to 0 pF to show an effect of output load on both on-chip and off-chip power consumption of FIR filter design. 20 nm technology based FVA1156 package and Kintex-7 family ultra-scale FPGA is taken under reconsideration for implementation of our model. With the use of HSTL_II IO standards, there is 84.39 and 92.83% reduction in IOs power when we scale down capacitance from 5000 to 500 and 0 pF respectively. With the use of HSTL_I_18 IO standards, there is 72.48 and 80.13% reduction in total on-chip power when we scale down capacitance from 5000 to 500 and 0 pF respectively. Along with IOs power and total on-chip power, we have also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.

14 citations

Book ChapterDOI
14 Oct 2022
TL;DR: In this paper , the authors examined the history of dimensional facts based on energetic-spectral image classification designs by using prepared and semi-directed classifiers to classify detached sensing images with particularized class labels.
Abstract: As image sensor electronics have progressed, and hyperspectral images have been used in a wide range of applications. In terms of recognizing the classes, a lot of research work has been done to extract useful information from the available unstructured knowledge database. The use of spectral and geographical datatypes in images can improve the classification precision. To improve the accuracy of the energetic-spectral snap analysis, combining dimensional and spectral data is a good idea. This research study examines the history of dimensional facts based on energetic-spectral image classification designs by using prepared and semi-directed classifiers to classify detached sensing images with particularized class labels. Long-term data are removed if the features are protensive. To increase the veracity of classification, the extracted traits are prepared by utilizing multiple classifiers. The preparation and sinking balance towards the loss function have been reused to train the classifiers. To avoid local minima, the preparation is approved by utilizing various tiers for accompanying the extra balancing limits. To overcome the risk of establishing a contradictory validity image, each detached perceiving image is classified throughout the experiment stage. Exploratory discoveries demand higher validity in-class criteria than other advanced directed classifier techniques.

10 citations

Journal ArticleDOI
TL;DR: This work scaled down the capacitance from 512pF to 32pF at various fixed frequency and implemented on 28 nm Artix7 FPGA with I/O Power & Leakage Power.
Abstract: Reducing the power consumption is the main concern in green computing. So here we used capacitance scaling technique on comparator for optimizing the power. We worked with I/O Power & Leakage Power because Clock Power & Signal Power are independent of capacitance scaling. In our work we have scaled down the capacitance from 512pF to 32pF at various fixed frequency. At 1GHz when we scale down the capacitance from 512pF to 32pF then we got 91.26% reduction in total I/O power dissipation. At 10 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.36% reduction in total I/O power dissipation. At 20 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.364% reduction in total I/O power dissipation. At 30 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.3624% reduction in total I/O power dissipation. At 40GHz when we scale down the capacitance from 512pF to 32pF then we got 91.36277% reduction in total I/O power dissipation. This design is implemented on 28 nm Artix7 FPGA.

8 citations

Journal ArticleDOI
TL;DR: The FIFO (First In First Out) circuit is designed and calculated its total power dissipation at different-different families of SSTL with frequency scaling techniques and is based on 28 nm kintex-7 FPGA family.
Abstract: for High Performance Processor of Portable Devices Abhay Saxena , Sanjeev Kumar Sharma , Pragya Agarwal Chandrashekhar Patel #4 #1,3,4 Department of Computer Science DSVV Haridwar, India 1 abhaysaxena2009@gmail.com 3 pragyaagarwal30@gmail.com shekharrockin1988@gmail.com *2 JP Institute of Engineering and Technology Meerut, India 2 dean.ar@jpiet.com Abstract— Now days green computing is major research area in the computer science field, where we want to reduce the total power consumption of our device by applying different techniques .Having this concern we have designed our FIFO (First In First Out) circuit and calculated its total power dissipation at different-different families of SSTL with frequency scaling techniques. In this technique we used following (20 GHz, 40GHz, 60 GHz and 80 GHz ) frequency range. In our work first we have worked with SSTL12 and found that when we scaled down the frequency from 80 GHz to 20 GHz 71.55% reduction in total IO power. In second we have worked with SSTL15 and got 74.02% of reduction in total IO power when we reduced frequency from 80 GHz to 20 GHz. In last we worked with SSTL18_I and SSTL18_II and found 74.29% and 74.28% of reduction in total power respectively, when we scaled down the frequency from 80 GHz to 20 GHz. We have designed our FIFO on 28 nm kintex-7 FPGA family

5 citations