Preston

Bio: Preston is an academic researcher from Carnegie Mellon University. The author has contributed to research in topics: Pattern recognition (psychology) & Data acquisition. The author has an hindex of 2, co-authored 2 publications receiving 64 citations.

Cellular Logic Computers for Pattern Recognition

Abstract: genealogy of cellular logic computers reveals an interesting diversity of architectures, but it took the IC technology of the seventies to significantly expand their practical applications. Cellular logic computers, under development since the 1950's, are now in use for image processing in hundreds of laboratories worldwide. This survey of cellular logic computer architectures for pattern processing in image analysis concentrates on recent efforts and examines some newer architectures that combine logical and numerical computations. A logical (or \"binary\") image is one in which the value of each picture element is a single bit. Such images are black and white, and they are processed or modified by use of logical rather than numerical transforms. Boolean algebra provides the mathematics for such transforms. This does not mean that so-called \"gray-level\" images cannot be processed by the cellular logic computer, or CLC. Any gray-level image can be consverted into a registered stack of binary images through multithresh-olding. After each member of the stack is processed logically, the stack can be returned to gray-level format by arithmetically summing the results. Whether the final output is generated faster or more economically by a CLC or by a computer system carrying out numerical computations depends upon (1) the number of binary images required in the stack, (2) the speed of thresholding, (3) the speed of the CLC itself, and (4) the speed of arithmetic recombination. Logical processing often has advantages over more traditional numerical methods in that multilevel, recur-sive logical transforms followed by arithmetic recom-bination have certain unique properties with respect to their use in image processing. Logical transforms can be considered as filters; many are constant phase, pass absolutely no signal beyond cutoff, and have a cutoff frequency that decreases inversely with the number of recur-sions. I Furthermore, logical transforms, when executed as convolution functions using small (say, 3 x 3) kernels, can be executed at ultra high speed (less than one nanose-cond per convolution step) by doing all computations by table lookup and paralleling lookup tables as well as pipelining the computational steps. Neighborhood functions Cellular logic computers are used for the digital computation of two-dimensional and, more recently, three-dimensional logical neighborhood functions in image processing. In general, a logical neighborhood function is one in which the output v alue of each picture element is a function of the original value of the element and the values of the directly adjacent neighbors of the …

Computing in Medicine

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HELP: A Dynamic Hospital Information System

Abstract: The HELP (Health Evaluation through Logical Processing) system is a computerized hospital information system developed by the authors at the LDS Hospital at the University of Utah, USA. It provides clinical, hospital administration and financial services through the use of a modular, integrated design. This book thoroughly documents the HELP system. Chapters discuss the use of the HELP system in intensive care units, the use of APACHE and APACHE II on the HELP system, various clinical applications and inactive or experimental HELP system modules.

Parallel architectures and algorithms for image component labeling

Abstract: A survey and a characterization of the various parallel algorithms and architectures developed for the problem of labeling digitized images over the last two decades are presented. It is shown that four basic parallel techniques underly the various parallel algorithms for this problem. However, because most of these techniques have been developed at a theoretical level, it is still not clear which techniques are most efficient in practical terms. Parallel architectures and parallel models of computation that implement these techniques are also studied. >

Adaptive instruction processing by array processor having processor identification and data dependent status registers in each processing element

Abstract: Equipping individual processing elements with an instruction adapter provides an array processor with adaptive spatial-dependent and data-dependent processing capability. The instruction becomes variable, at the processing element level, in response to spatial and data parameters of the data stream. An array processor can be optimized, for example, to carry out very different instructions on spatial-dependent data such as blank margin surrounding the black lines of a sketch. Similarly, the array processor can be optimized for data-dependent values, for example to execute different instructions for positive data values than for negative data values. Providing each processing element with a processor identification register permits an easy setup by flowing the setup values to the individual processing elements, together with setup of condition control values. Each individual adaptive processing element responds to the composite values of original setup and of the data stream to derive the instruction for execution during the cycle. In the usual operation, each adaptive processing element is individually addressed to set up a base instruction; it also is conditionally set up to execute a derived instruction instead of the base instruction. An array processor made up of adaptive processing elements can adapt dynamically to changes in its input data stream, and thus can be dynamically optimized, resulting in greatly enhanced performance at very low incremental cost.