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Pritha Banerjee

Bio: Pritha Banerjee is an academic researcher from University of Calcutta. The author has contributed to research in topics: Netlist & Placement. The author has an hindex of 2, co-authored 9 publications receiving 86 citations.

Papers
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Proceedings ArticleDOI
29 May 2013
TL;DR: This paper proposes the first academic multilevel timing-and-wirelength-driven analytical placement algorithm for FPGAs, which can achieve 6.91 × speedup on average with 7% smaller critical path delay and 1% shorter routed wirelength compared to VPR, the well-known, state-of-the-art academic simulated-annealing-based FPGA placer.
Abstract: The increasing design complexity of modern circuits has made traditional FPGA placement techniques not efficient anymore. To improve the scalability, commercial FPGA placement tools have started migrating to analytical placement. In this paper, we propose the first academic multilevel timing-and-wirelength-driven analytical placement algorithm for FPGAs. Our proposed algorithm consists of (1) multilevel timing-and-wirelength-driven analytical global placement with the novel block alignment consideration, (2) partitioning-based legalization, (3) wirelength-driven block matching-based detailed placement, and (4) timing-driven simulated-annealing-based detailed placement. Experimental results show that our proposed approach can achieve 6.91 × speedup on average with 7% smaller critical path delay and 1% shorter routed wirelength compared to VPR, the well-known, state-of-the-art academic simulated-annealing-based FPGA placer.

43 citations

Journal ArticleDOI
TL;DR: A global floorplan generation method PartialHeteroFP is proposed to obtain same positions for the common modules across all instances such that the heterogeneous resource requirements of all modules in each instance are satisfied, and the total half-perimeter wirelength over all instances is minimal.
Abstract: Partial reconfiguration on heterogeneous field-programmable gate arrays with millions of gates yields better utilization of its different types of resources by swapping in and out the appropriate modules of one or more applications at any instant of time. Given a schedule of sub-task instances where each instance is specified as a netlist of active modules, reconfiguration overhead can be reduced by fixing the position and shapes of modules common across all instances. We propose a global floorplan generation method PartialHeteroFP to obtain same positions for the common modules across all instances such that the heterogeneous resource requirements of all modules in each instance are satisfied, and the total half-perimeter wirelength over all instances is minimal. Experimental results establish that the proposed PartialHeteroFP produces floorplans very fast, with 100% match of common modules and thereby minimizing the partial reconfiguration overhead.

42 citations

Proceedings ArticleDOI
01 Nov 2017
TL;DR: This work minimizes stitch unfriendly patterns at post-layout stage based on perturbation of wire segments by formulating it as a maximum matching problem, thereby making an already optimized design more MEBL friendly without increasing the wirelength.
Abstract: Soaring distortions for immersion lithography with 193nm wavelength has necessiated the Next Generation Lithography (NGLs) such as Electron Beam Lithography (EBL). While single e-beam lithography suffers from very low throughput, Multiple Electron Beam Lithography (MEBL) improves it by writing with multiple e-beams in parallel, each dedicated to a disjoint region called a vertical stripe. However, layout patterns, in particular routing segments, vias and short polygons crossing over stripe boundary (stitch line) causes severe pattern distortion leading to malfunctioning of the chip. We minimize these stitch unfriendly patterns at post-layout stage based on perturbation of wire segments by formulating it as a maximum matching problem. Experimental results comprise two variants of perturbations of wire segments. Each variant shows significant minimization of stitch unfriendly patterns, thereby making an already optimized design more MEBL friendly without increasing the wirelength.

6 citations

Proceedings ArticleDOI
02 Nov 2015
TL;DR: This paper proposes an Integer Linear Programming based method to mitigate the effects of flare in the post routing step through perturbation of wire segments, which shows significant reduction of flare and its standard deviation across the chip surface.
Abstract: With growing demand for complex and high density integrated chips (IC), optical lithography with 193 nm immersion technology has become a bottleneck in the chip manufacturing industry. IC fabrication industry is looking forward to next generation lithography methods, for example, Extreme Ultraviolet Lithography (EUVL). While EUVL is capable of printing with a wavelength of 13.5 nm, it suffers from a major drawback called flare, due to the scattering of light on blank surfaces. Large flare and/or its large variation cause critical dimension (CD) violations. In this paper, we propose an Integer Linear Programming based method to mitigate the effects of flare in the post routing step through perturbation of wire segments. Experimental results on a set of synthetic circuits show significant reduction of flare and its standard deviation across the chip surface.

3 citations

Proceedings ArticleDOI
13 Apr 2011
TL;DR: Experimental results show that on the average there is negligible deviation in cut-size for multi-constraint bipartitioning a netlist of modules having m types of heterogeneous resources, as in modern FPGAs with configurable logic blocks, Block RAMs and Multipliers (MULs).
Abstract: In this paper, we present a heuristic algorithm for bipartitioning a netlist of modules having m types of heterogeneous resources, as in modern FPGAs with configurable logic blocks (CLBs), Block RAMs and Multipliers (MULs). The desired min-cut bipartition has to satisfy m constraints arising from given balance ratios, one for each type of resource. The netlist is represented as a hypergraph, whose vertices correspond to the modules. Each vertex has a m-tuple weight vector, denoting the number of resource units of each type. Our proposed multi-constraint bipartitioner is based on dynamic programming, which employs a single-constraint bipartitioner. The upper bounds for mean deviation in combined balance ratio, and for the increment in cut-size are presented. Experimental results on a set of benchmarks show that on the average there is negligible deviation in cut-size for multi-constraint bipartitions from single-constraint bipartion, while satisfying the individual balance ratio constraints for each type of resource.

2 citations


Cited by
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Journal ArticleDOI
TL;DR: This work reviews FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures, and investigates design flows and identifies the key challenges in making reconfigurable FPGAs systems easier to design.
Abstract: Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption.

122 citations

Book ChapterDOI
19 Mar 2012
TL;DR: This paper introduces a technique which can be incorporated into the existing tool flow that overcomes the need for manual floorplanning for PR designs, and takes into account overheads generated due to PR as well as the architecture of the latest FPGAs.
Abstract: Partial reconfiguration (PR) has enabled the adoption of FPGAs in state of the art adaptive applications. Current PR tools require the designer to perform manual floorplanning, which requires knowledge of the physical architecture of FPGAs and an understanding of how to floorplan for optimal performance and area. This has lead to PR remaining a specialist skill and made it less attractive to high level system designers. In this paper we introduce a technique which can be incorporated into the existing tool flow that overcomes the need for manual floorplanning for PR designs. It takes into account overheads generated due to PR as well as the architecture of the latest FPGAs. This results in a floorplan that is efficient for PR systems, where reconfiguration time and area should be minimised.

58 citations

Proceedings ArticleDOI
07 Nov 2016
TL;DR: An FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routability and a novel physical and congestion aware packing algorithm and a hierarchical detailed placement technique are proposed.
Abstract: FPGA packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose a FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routability. A novel physical and congestion aware packing algorithm and several congestion aware detailed placement techniques are proposed. Compared with the top 3 winners of ISPD'16 FPGA placement contest, UTPlaceF can achieve 3.3%, 7.7% and 28.3% better routed wirelength with similar or shorter runtime.

52 citations

Proceedings ArticleDOI
07 Nov 2016
TL;DR: This paper proposes a routability-driven placement algorithm for large-scale heterogeneous FPGAs that can give routable placement results for all the benchmarks in the ISPD2016 contest and can achieve good result compared to the other wining teams of the IS PD2016 contest.
Abstract: As the complexity and scale of FPGA circuits grows, resolving routing congestion becomes more important in FPGA placement. In this paper, we propose a routability-driven placement algorithm for large-scale heterogeneous FPGAs. Our proposed algorithm consists of (1) partitioning, (2) packing, (3) global placement with congestion estimation, (4) window-base legalization, and (5) routing resource-aware detailed placement. Experimental results show that our proposed approach can give routable placement results for all the benchmarks in the ISPD2016 contest and can achieve good result compared to the other wining teams of the ISPD2016 contest.

49 citations

Journal ArticleDOI
TL;DR: A novel physical and congestion aware packing algorithm and several congestion aware detailed placement techniques are proposed that simultaneously optimizes wirelength and routability in an FPGA packing and placement engine called UTPlaceF.
Abstract: Field programmable gate array (FPGA) packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose an FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routability. A novel physical and congestion aware packing algorithm and a hierarchical detailed placement technique are proposed. UTPlaceF outperforms state-of-the-art FPGA placers simultaneously in runtime and solution quality on International Symposium on Physical Design (ISPD) 2016 benchmark suite. Compared with the top three winners of ISPD’16 FPGA placement contest, UTPlaceF can deliver 6.2%, 11.6%, and 29.1% better routed wirelength with shorter runtime.

35 citations