International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

This paper proposes single walled carbon nanotube bundles as VLSI interconnects at 20nm, 16nm, 14nm and 12nm Technology nodes. Effects of voltage scaling on propagation delay and power dissipation of the interconnects is analyzed. Input voltages ranging from 0.3 V (deep subthreshold) to 0.8 V (moderate subthreshold) are considered. After formulating the equivalent single conductor RLC transmission line circuit of the interconnects, simulations of a driver-interconnect-load setup using SmartSPICE was carried out. Later, electric field simulations of coupled interconnects considering Miller capacitance effects for in-phase and out-of-phase conditions was done. Results show that voltage scaling is essential as the technology node size decreases to ensure low-power devices.

Priyamanga Bhardwaj

Papers

Single Walled Carbon Nanotube Interconnects For Future Integrated Circuits