An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

Current-steering logic (CSL) and current-balanced logic (CBL) are logic families that have been proposed with the objective of reducing the substrate noise in mixed-signal integrated circuits. These two families are compared here with conventional CMOS by simulation, using a substrate model extracted from the layouts, and also by measurements on a test chip. With small, low-power cells, noise reduction of CSL and CBL with respect to CMOS is only marginal; the same result is obtained with large, high-power (buffer) cells, if the supply wire inductance is very low. For large cells with typical wire bonding supply inductance (of the order of 10 nH), CBL cells provide significant noise reduction and are more effective than CSL cells; these become even noisier than CMOS cells for large inductance values. The results here, considering the real substrate noise, are more reliable than previous evaluations considering only the amplitude of the supply current spikes.

A comparison by simulation and by measurement of the substrate noise generated by CMOS, CSL, and CBL digital circuits

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Wideband High-Performance Sigma-Delta Modulators for High-Speed Communications

The reduction in supply voltage, loss of dynamic range and increased noise prevent the analog circuits from taking advantage of advanced technologies. Therefore the trend is to move all signal processing tasks to digital domain where advantages of technology scaling can be used. Due to this, there exists a need for data converters with large signal bandwidths, higher speeds and greater dynamic range to act as an interface between real world analog and digital signals. 

The Delta Sigma (∆Σ) modulator is a data converter that makes use of large sampling rates and noise shaping techniques to achieve high resolution in the band of interest. The modulator consists of analog integrators and comparators which create a modulated digital bit stream whose average represents the input value. Due to their simplicity, they are popular in narrow band receivers, medical and sensor applications. 

However Operational Amplifiers (Op-Amps) or Operational Transconductance Amplifiers (OTAs), which are commonly used in data converters, present a bottleneck. Due to low supply voltages, designers rely on folded cascode, multistage cascade and bulk driven topologies for their designs. Although the two stage or multistage cascade topologies offer good gain and bandwidth, they suffer from stability problems due to multiple stages and feedback requiring large compensation capacitors. Therefore other low voltage Switched-Capacitor (SC) circuit techniques were developed to overcome these problems, based on inverters, comparators and unity gain buffers. 

In this thesis we present an alternative approach to design of ∆Σ modulators using Second Generation Current Conveyors (CCIIs). The important feature of these modulators is the replacement of the traditional Op-Amp based SC integrators with CCII based SC integrators. The main design issues such as the effect of the non-idealities in the CCIIs are considered in the operation of SC circuits and solutions are proposed to cancel them. Design tradeoffs and guidelines for various components of the circuit are presented through analysis of existing and the proposed SC circuits. A two step adaptive calibration technique is presented which uses few additional components to measure the integrator input output characteristic and linearize it for providing optimum performance over a wide range of sampling frequencies while maintaining low power and area.

The presented CCII integrator and calibration circuit are used in the design of a 4th order (2-2 cascade) ∆Σ modulator which has been fabricated in UMC 90nm/1V technology through Europractice. Experimental values for Signal to Noise+Distortion Ratio (SNDR), Dynamic Range (DR) and Figure Of Merit (FOM) show that the modulator can compete with state of art reconfigurable Discrete-Time (DT) architectures while using lower gain stages and less design complexity.

Analysis of Current Conveyor based Switched Capacitor Circuits for Application in ∆Σ Modulators

This chapter gives an overview of reported cutting-edge ?> ?> modulator ICs fabricated in CMOS technologies. The main purpose of this overview is to make an exhaustive analysis of the evolution trends, design challenges, and reported solutions in order to extract practical conclusions and guidelines which may be useful for designers in their own projects. The chapter gives an overview of the state-of-the-art ?> ?>Ms, comparing their performance with Nyquist-rate ADCs. The diverse families of ?> ?>M architectures and circuit techniques are exhaustively analyzed and compared in order to extract practical and empirical design guidelines. Then, it reviews some of the most significant cutting-edge ?> ?>M techniques, analyzing the design trends and challenges in the frontiers of ?> ?>Ms. The chapter concludes with a classified description of state-of-the-art references.

Frontiers of Modulators: Trends and Challenges

In this paper the design and measured results of a fourth-order sigma-delta A/D converter is presented Signal scaling technique was used to alleviate its large signal overload problem and maximize the allowable input signal level, which also increases the maximum output signal-to-noise ratio A low noise current steering logic was used to design digital noise cancellation logic, which reduces the digital coupling noise and simplifies the circuit layout The experimental chip was implemented with a 3 /spl mu/m CMOS technology and operated from a single 5 V power supply With an oversampling ratio of 64, it achieves 91 dB dynamic range and 50 kHz conversion speed The peak signal-to-noise ratio is 88 dB The test results were bounded by the quality of the input signal source

Pushan Tang

Papers

An oversampled A/D converter using cascaded fourth order sigma-delta modulation and current steering logic