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Qinghang Zhao

Bio: Qinghang Zhao is an academic researcher from Tsinghua University. The author has contributed to research in topics: Logic gate & Transistor. The author has an hindex of 5, co-authored 11 publications receiving 74 citations.

Papers
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Journal ArticleDOI
TL;DR: A user-friendly tool was developed to provide an interactive way for convenient parameter extraction and the model is continuous from the off-state and subthreshold regimes to the above-threshold regime, avoiding the convergence problems when being used in SPICE circuit simulations.
Abstract: Thin-film transistors (TFT) in hydrogenated amorphoussilicon, amorphousmetal oxide, andsmallmolecule and polymer organic semiconductors would all hold promise as potential device candidates to large area flexible electronics applications. A universal compact dc model was developed with a proper balance between the physical and mathematical approaches for these thin-film transistors (TFTs). It can capture the common key parameters used for device performance benchmarking of the different TFTs while being applicable to a wide range of TFT technologies in different materials and device structures. Based on this model, a user-friendly tool was developed to provide an interactive way for convenient parameter extraction. The model is continuous from the off-state and subthreshold regimes to the above-threshold regime, avoiding the convergence problems when being used in SPICE circuit simulations. Finally, for verification, it was implemented into a SPICE circuit simulator using Verilog-A to simulate a TFT circuit examplewith the simulated results agreeing verywell with the experimental measurements.

31 citations

Proceedings ArticleDOI
09 Mar 2015
TL;DR: This work proposes a novel holistic backup flow, which consists of a partial backup process and a run-time pre- writeback scheme for nvSRAM based caches, and presents an adaptive pre-writeback point allocation strategy to further reduce the backup load.
Abstract: In modern energy harvesting sensor nodes, nonvolatile SRAM (nvSRAM) has been widely investigated as a promising on-chip memory architecture because of its zero standby power, resilience to power failures, and fast read/write operations. However, conventional approaches transfer all data from SRAM into NVM during the backup process. Thus, large on-chip energy storage capacitors are normally required. In addition, high peak inrush current is generated instantaneously, which has a negative impact on energy efficiency and circuit reliability. To mitigate these problems, we propose a novel holistic backup flow, which consists of a partial backup process and a run-time pre-writeback scheme for nvSRAM based caches. A statistics based dead-block predictor is employed to achieve a fast and low power partial backup process. We also present an adaptive pre-writeback point allocation strategy to further reduce the backup load. Simulation results show that, with our proposed backup scheme, energy storage capacitance is reduced by 34% and inrush current is reduced by 54% on average compared to the conventional full backup scheme.

23 citations

Journal ArticleDOI
TL;DR: A holistic data backup optimization to mitigate problems in nvSRAM, consisting of a partial backup algorithm and a run-time adaptive write policy and an adaptive policy is used to switch between write-back and write-through strategy to reduce the rollback induced by backup failures.
Abstract: Nonvolatile static random access memory (nvSRAM) has been widely investigated as a promising on-chip memory architecture in energy harvesting sensor nodes, due to zero standby power, resilience to power failures, and fast read/write operations. However, conventional approaches back up all data from static random access memory into nonvolatile memory when power failures happen. It leads to significant energy overhead and peak inrush current, which has a negative impact on the system performance and circuit reliability. This paper proposes a holistic data backup optimization to mitigate these problems in nvSRAM, consisting of a partial backup algorithm and a run-time adaptive write policy. A statistic dead-block predictor is employed to achieve dead block identification with trivial hardware overhead. An adaptive policy is used to switch between write-back and write-through strategy to reduce the rollback induced by backup failures. Experimental results show that the proposed scheme improves the performance by 4.6% on average while the backup power consumption and the inrush current are reduced by 38.1% and 54% on average compared to the full backup scheme. What is more, the backup capacitor size for energy buffer can be reduced by 40% on average under the same performance constraint.

15 citations

Journal ArticleDOI
TL;DR: In this article, the analytical noise margin model for the zero-$V_{\text {GS}}$ load TFT NAND gate and NOR gate is derived and based on that, a simple, accurate, and highly scalable yield model for combinational TFT logic circuits based on standard cell library is further proposed.
Abstract: The flexible electronics is promising in the area of the Internet of Things and wearable devices and the thin-film transistor (TFT) technologies are crucial for flexible electronics. Among them, the zero- $V_{\text {GS}}$ load TFT circuits are widely used for its simple structure and high gain merits. However, the yield model is lacking for zero- $V_{\text {GS}}$ load TFT circuits. In this paper, the analytical noise margin model for the zero- $V_{\text {GS}}$ load TFT NAND gate and NOR gate is derived. Based on that, a simple, accurate, and highly scalable yield model for the combinational TFT logic circuits based on standard cell library is further proposed. ISCAS’85 benchmark circuits are used to validate the yield model. Compared with Monte Carlo simulation, the model achieves 3–4 orders of magnitude speedup with comparative results.

9 citations

Journal ArticleDOI
TL;DR: In this paper, the authors derived the noise margin (NM), delay, and power models for pseudo-CMOS logic circuits, and simplified those models formanual analysis and design optimization.
Abstract: Flexibleelectronics based on thin-film transistors (TFTs) are promising in the area of Internet of Things and wearable devices, where the pseudo-CMOS logic is widely used in the unipolar TFT circuits Though plenty of device models exist, analytical circuit-level models are still absent, preventing the further development of design and analysis of flexible TFT circuits In this paper, we derive the noise margin (NM), delay, and power models for pseudo-CMOS logic circuits Furthermore, we simplify thosemodels formanual analysis and design optimization Allmodels are validated by SPICE simulations, where the device model and its parameters are extracted from the fabricated self-assembled monolayer organic TFTs The average errors for NM, delay, and power models are 3%, 10%, and 3%, respectively In addition, we exploit the delay models in a voltage-controlled oscillator design and its linearity of frequency characteristic is optimized with the proposed models, demonstrating their effectiveness

7 citations


Cited by
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Journal ArticleDOI
TL;DR: This paper provides a comprehensive review of the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.
Abstract: Attributed to its advantages of super mechanical flexibility, very low-temperature processing, and compatibility with low cost and high throughput manufacturing, organic thin-film transistor (OTFT) technology is able to bring electrical, mechanical, and industrial benefits to a wide range of new applications by activating nonflat surfaces with flexible displays, sensors, and other electronic functions. Despite both strong application demand and these significant technological advances, there is still a gap to be filled for OTFT technology to be widely commercially adopted. This paper provides a comprehensive review of the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.

204 citations

Proceedings ArticleDOI
07 Jun 2015
TL;DR: New metrics of nonvolatile processors to consider energy harvesting factors for the first time are proposed and the nonvolatility processor design from circuit to system level is explored.
Abstract: Energy harvesting is gaining more and more attentions due to its characteristics of ultra-long operation time without maintenance. However, frequent unpredictable power failures from energy harvesters bring performance and reliability challenges to traditional processors. Nonvolatile processors are promising to solve such a problem due to their advantage of zero leakage and efficient backup and restore operations. To optimize the nonvolatile processor design, this paper proposes new metrics of nonvolatile processors to consider energy harvesting factors for the first time. Furthermore, we explore the nonvolatile processor design from circuit to system level. A prototype of energy harvesting nonvolatile processor is set up and experimental results show that the proposed performance metric meets the measured results by less than 6.27% average errors. Finally, the energy consumption of nonvolatile processor is analyzed under different benchmarks.

127 citations

Journal ArticleDOI
06 Sep 2019
TL;DR: This review will present the state of the art in thin-film electronics and demonstrate examples of low-cost printable transistors and biosensors that are flexible/stretchable for wearable and other applications and a concept for an integrated system comprising sensors and interfacing circuits that has the potential to enable batteryless operation.
Abstract: Thin-film electronics has hugely benefitted from low-cost processes, large-area processability, and multifunctionality. This has not only stimulated innovation in display and sensor technology but has also demonstrated great potential for the integration of components for human–machine interfaces. For electronics to be deployed as sensor interfaces and signal processing, the quest for low power is compelling due to the inherently limited battery lifetime. This review will present the state of the art in thin-film electronics and demonstrate examples of low-cost printable transistors and biosensors that are flexible/stretchable for wearable and other applications. Ultralow-power design for thin-film transistors will be discussed from the standpoint of reducing both operating voltage and operating current, taking into account the challenges in meeting frequency requirements. Compact models for circuit design will be reviewed along with new insights into ultralow-power transistors and high-gain amplifier circuits. Finally, a concept for an integrated system comprising sensors and interfacing circuits will be demonstrated, which has the potential to enable batteryless operation.

43 citations

Journal ArticleDOI
TL;DR: This paper is the first work to improve the system-level sleep/wake-up speed of an energy harvesting NVP and improves the robustness of the NVP to power fluctuations but also brings significant advantages for better utilization of harvested energy.
Abstract: Nonvolatile processor (NVP) attracts more and more attentions for its immunity to power loss in energy harvesting scenarios The overall performance of an NVP is determined by its sleep and wake-up speeds, which refer to how fast the NVP can turn itself off and on when a sudden power failure occurs To the best of our knowledge, this paper is the first work to improve the system-level sleep/wake-up speed of an energy harvesting NVP A hybrid CMOS/ferroelectric nonvolatile flip-flop (nvFF) and a high-speed voltage detector are designed and integrated in the proposed NVP to jointly minimize its sleep and wake-up time Measurement results demonstrate $46~\mu \text {s}$ wake-up time and $14~\mu \text {s}$ sleep time, which is up to 18 and 24 times speedup over existing works This approach not only improves the robustness of the NVP to power fluctuations but also brings significant advantages for better utilization of harvested energy

40 citations

Proceedings ArticleDOI
01 Oct 2016
TL;DR: In this paper, the authors proposed replacement and checkpoint policies for SRAM and NVM based hybrid cache in NVPs whose execution is interrupted frequently, and the experimental results show that the proposed architectures and polices outperform existing cache architectures for NVP.
Abstract: Energy harvesting is one of the most promising battery alternatives to power future generation embedded systems in Internet of Things (IoT). However, energy harvesting powered embedded systems suffer from frequent execution interruption due to unstable energy supply. To bridge intermittent program execution across different power cycles, non-volatile processor (NVP) was proposed to checkpoint register contents during power failure. Together with register contents, the cache contents also need to be preserved during power failure. While pure non-volatile memory (NVM) based cache is an intuitive option, it suffers from inferior performance due to high write latency and energy overhead. In this paper, we will propose replacement and checkpoint policies for SRAM and NVM based hybrid cache in NVPs whose execution is interrupted frequently. Checkpointing aware cache replacement polices and smart checkpointing polices are proposed to achieve satisfactory performance and efficient checkpointing upon a power failure and fast resumption when power returns. The experimental results show that the proposed architectures and polices outperform existing cache architectures for NVPs.

35 citations