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Quang-Kien Trinh

Bio: Quang-Kien Trinh is an academic researcher from Le Quy Don Technical University. The author has contributed to research in topics: Computer science & Distortion. The author has an hindex of 4, co-authored 21 publications receiving 82 citations. Previous affiliations of Quang-Kien Trinh include National University of Singapore.

Papers
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Journal ArticleDOI
TL;DR: A novel boosted voltage sensing (BVS) scheme is proposed that substantially improves the resiliency of STT-MRAMs against variations in read accesses based on bitline voltage sensing, and on a wide range of voltages.
Abstract: This paper proposes a novel boosted voltage sensing (BVS) scheme that substantially improves the resiliency of STT-MRAMs against variations in read accesses based on bitline voltage sensing, and on a wide range of voltages. The BVS scheme mitigates the impact of variations in the senseamp and the reference voltage generation, and is based on switched-capacitor voltage boosters. The related area-performance-energy-resiliency tradeoff is explored, and design guidelines are derived to improve the read margin at minimum overhead.

30 citations

Journal ArticleDOI
TL;DR: This paper proposes a novel approach to enhance the STT-MRAMs read margin based on the concept of dynamic reference, aiming to widen the difference between the bitline and the reference voltage, thus improving the read robustness and substantially reducing the read failure rate.
Abstract: This paper proposes a novel approach to enhance the STT-MRAMs read margin based on the concept of dynamic reference (DR) Our dynamic reference scheme dynamically adjusts the sense amplifier reference voltage according to the bitline voltage, aiming to widen the difference between the bitline and the reference voltage (ie, the read margin) As a result, larger variations can be accommodated, thus improving the read robustness and substantially reducing the read failure rate This DR scheme does not require any change in the bitcell and requires minimal modifications of conventional arrays, hence it can be jointly used with existing assist techniques enhancing the read robustness From Monte Carlo simulations in 65 nm, the proposed DR scheme improves the read bit error rate by two orders of magnitude across a wide range of voltages (075–12 V) compared with the conventional voltage sensing scheme This is achieved at 03% area overhead, less than 15% performance degradation, and less than 25% energy penalty Furthermore, the joint adoption of the DR approach and switched-cap bitline boosting further reduces the sense amplifier area by 25% at iso-failure rate, and reduces the energy by 6–10% compared with the standalone DR

26 citations

Journal ArticleDOI
TL;DR: Results show that the write energy reduction achieved through voltage scaling strongly depends on the adopted bitcell, and was found to be up to 20%-30% in a 65-nm and 28-nm array.
Abstract: This paper investigates the impact of voltage scaling on energy and performance of STT-MRAM arrays under write access, which is well known to be energy critical. Simple analytical models of energy and delay are introduced to gain an insight into the energy-performance tradeoff at low voltages, and minimum-energy operation. The minimum-energy point is found to lie at voltages that are substantially higher than CMOS logic and memories. The impact of voltage scaling on the area-energy-performance tradeoff on most representative STT-MRAM bitcells is investigated and justified through the proposed models. Interestingly, bitcell area optimization is shown to enable 25%–40% energy savings compared to minimum-sized bitcells, when operating at low voltages. Results show that the write energy reduction achieved through voltage scaling strongly depends on the adopted bitcell, and was found to be up to 20%–30% in a 65-nm and 28-nm array. Voltage scaling is expected to become mainstream in STT-MRAM design, as promising approach to mitigate the well-known issue of large write energy consumption.

22 citations

Journal ArticleDOI
TL;DR: Compared to other sensing schemes at iso-BER, the proposed TBS scheme achieves a more favorable area-robustness-energy-performance tradeoff.
Abstract: This paper introduces the concept of time-based sensing (TBS) for bitcell read in spin transfer torque magnetic RAMs arrays. The TBS scheme converts the bitline voltage into time, then the sense amplifier discriminates the two bitcell levels in the time domain. The TBS scheme substantially improves the read yield compared to conventional voltage sensing (CVS). As further advantage, TBS requires no analog reference generation and distribution by leveraging the implicit timing reference set by the gate delay in the sense amplifier. Monte Carlo simulations in 65 nm show that the proposed TBS improves the read bit error rate (BER) by two-three orders of magnitude, compared to CVS. This is achieved at the cost of less than 1% area penalty and 13–14% performance degradation, and insignificant (2%) energy penalty when designed at iso-area (minimum delay). Compared to other sensing schemes at iso-BER, the proposed TBS scheme achieves a more favorable area-robustness-energy-performance tradeoff.

20 citations

Journal ArticleDOI
TL;DR: The proposed architecture allows to perform unrestricted accumulation across rows for full utilization of the array and BNN model scalability, and overcomes challenges on the sensing circuit due to the limitation of low regular tunneling magnetoresistance ratio (TMR) in STT-MRAM.
Abstract: This paper presents a novel architecture for in-memory computation of binary neural network (BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are fed through bitlines, then, a BNN vector multiplication can be done by single sensing of the merged SL voltage of a row. Our design allows to perform unrestricted accumulation across rows for full utilization of the array and BNN model scalability, and overcomes challenges on the sensing circuit due to the limitation of low regular tunneling magnetoresistance ratio (TMR) in STT-MRAM. Circuit techniques are introduced in the periphery to make the energy-speed-area-robustness tradeoff more favorable. In particular, time-based sensing (TBS) and boosting are introduced to enhance the accuracy of the BNN computations. System simulations show 80.01% (98.42%) accuracy under the CIFAR-10 (MNIST) dataset under the effect of local and global process variations, corresponding to an 8.59% (0.38%) accuracy loss compared to the original BNN software implementation, while achieving an energy efficiency of 311 TOPS/W.

12 citations


Cited by
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01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.

1,038 citations

01 Jan 2016
TL;DR: The logical effort designing fast cmos circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for reading logical effort designing fast cmos circuits. As you may know, people have search numerous times for their chosen novels like this logical effort designing fast cmos circuits, but end up in infectious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they are facing with some harmful bugs inside their desktop computer. logical effort designing fast cmos circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our book servers hosts in multiple locations, allowing you to get the most less latency time to download any of our books like this one. Merely said, the logical effort designing fast cmos circuits is universally compatible with any devices to read.

137 citations

Journal ArticleDOI
TL;DR: This brief presents a review of developments in spin-transfer-torque magnetoresistive random access memory (STT-MRAM) sensing over the past 20 years from a circuit design perspective and key breakthroughs for achieving the optimal reference scheme, read disturbance prevention, read energy reduction, accurate yield estimation, and overcoming other non-idealities are discussed.
Abstract: This brief presents a review of developments in spin-transfer-torque magnetoresistive random access memory (STT-MRAM) sensing over the past 20 years from a circuit design perspective. Various sensing schemes are categorized and described according to the data-cell variation-tolerant characteristics, pre-amplifiers, and offset tolerance. Key breakthroughs for achieving the optimal reference scheme, read disturbance prevention, read energy reduction, accurate yield estimation, and overcoming other non-idealities are discussed. This review is intended to facilitate further enhancement of STT-MRAM sensing in advanced technology nodes, thereby fulfilling STT-MRAM’s potential as a universal memory.

40 citations

Journal ArticleDOI
TL;DR: In this article, a time-domain CIM (TD-CIM) scheme using spintronics is presented to construct the energy-efficient convolutional neural network (CNN).
Abstract: The data transfer bottleneck in Von Neumann architecture owing to the separation between processor and memory hinders the development of high-performance computing. The computing in memory (CIM) concept is widely considered as a promising solution for overcoming this issue. In this article, we present a time-domain CIM (TD-CIM) scheme using spintronics, which can be applied to construct the energy-efficient convolutional neural network (CNN). Basic Boolean logic operations are implemented through recording the bit-line output at different moments. A multi-addend addition mechanism is then introduced based on the TD-CIM circuit, which can eliminate the cascaded full adders. To further optimize the compatibility of TD-CIM circuit for CNN, we also propose a quantization method that transforms floating-point parameters of pre-trained CNN models into fixed-point parameters. Finally, we build a TD-CIM architecture integrating with a highly reconfigurable array of field-free spin-orbit torque magnetic random access memory (SOT-MRAM) and evaluate its benefits for the quantized CNN. By performing digit recognition with the MNIST dataset, we find that the delay and energy are respectively reduced by 1.2-2.7 times and $2.4\times 10 ^{3} - 1.1\times 10 ^{4}$ times compared with STT-CIM and CRAM based on spintronic memory. Finally, the recognition accuracy can reach 98.65% and 91.11% on MNIST and CIFAR-10, respectively.

40 citations

Proceedings ArticleDOI
26 May 2019
TL;DR: An MRAM-based deep in-memory architecture (MRAM-DIMA) to efficiently implement multi-bit matrix vector multiplication for deep neural networks using a standard MRAM bitcell array is presented.
Abstract: This paper presents an MRAM-based deep in-memory architecture (MRAM-DIMA) to efficiently implement multi-bit matrix vector multiplication for deep neural networks using a standard MRAM bitcell array. The MRAM-DIMA achieves an 4.5 × and 70× lower energy and delay, respectively, compared to a conventional digital MRAM architecture. Behavioral models are developed to estimate the impact of circuit non-idealities, including process variations, on the DNN accuracy. An accuracy drop of ≤ 0.5% (≤ 1%) is observed for LeNet-300-100 on the MNIST dataset (a 9-layer CNN on the CIFAR-10 dataset), while tolerating 24% (12%) variation in cell conductance in a commercial 22 nm CMOS-MRAM process.

38 citations