Quming Zhou

Bio: Quming Zhou is an academic researcher from Rice University. The author has contributed to research in topics: Combinational logic & Logic gate. The author has an hindex of 9, co-authored 14 publications receiving 732 citations. Previous affiliations of Quming Zhou include Baker Hughes.

Gate sizing to radiation harden combinational logic

Abstract: A gate-level radiation hardening technique for cost-effective reduction of the soft error failure rate in combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve cost-effective tradeoffs between overhead and soft error failure rate reduction. The asymmetry in the logical masking probabilities at a gate is leveraged by decoupling the physical from the logical (Boolean) aspects of soft error susceptibility of the gate. Gates are hardened to single-event upsets (SEUs) with specified worst case characteristics in increasing order of their logical masking probability, thereby maximizing the reduction in the soft error failure rate for specified overhead costs (area, power, and delay). Gate sizing for radiation hardening uses a novel gate (transistor) sizing technique that is both efficient and accurate. A full set of experimental results for process technologies ranging from 180 to 70 nm demonstrates the cost-effective tradeoffs that can be achieved. On average, the proposed technique has a radiation hardening overhead of 38.3%, 27.1%, and 3.8% in area, power, and delay for worst case SEUs across the four process technologies.

Transistor sizing for radiation hardening

Abstract: This paper presents an efficient and accurate numerical analysis technique to simulate single event upsets (SEUs) in logic circuits. Experimental results that show the method is accurate to within 10% of the results obtained using SPICE are provided. The proposed method is used to study the ability of a CMOS gate to tolerate SEUs as a function of injected charge and transistor sizing (aspect ratio W/L). A novel radiation hardening technique to calculate the minimum transistor size required to make a CMOS gate immune to SEUs is also presented. The results agree well with SPICE simulations, while allowing for very fast analysis. The technique can be easily integrated into design automation tools to harden sensitive portions of logic circuits.

Cost-effective radiation hardening technique for combinational logic

Abstract: A radiation hardening technique for combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve cost-effective tradeoffs between overhead and soft error failure rate reduction. The technique, which decouples the physical from the logical aspects of soft error susceptibility of a gate, uses a gate (transistor) sizing technique that is both efficient and accurate (in comparison to SPICE). A full set of experimental results demonstrate the cost-effective tradeoffs that can be achieved.

Parallel domain decomposition for simulation of large-scale power grids

Abstract: This paper presents fully parallel domain decomposition (DD) techniques for efficient simulation of large-scale linear circuits such as power grids. DD techniques that use non-overlapping and overlapping partitioning of power grids are described in this paper. Simulation results show that with the proposed parallel DD framework, existing linear circuit simulators can be extended to handle large-scale power grids. Results for circuits with more than four million nodes indicate that parallel DD with LU factorization is most suitable for power grid simulation. However, for densely connected power grids, parallel DD with additive Schwarz preconditioning offers maximum scalability and best performance.

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model -- in posynomial form -- is integrated with performance and power constraints into an optimization framework based on geometric programming for design space exploration. Simulation results for design optimization using simultaneous dual- VDD and gate sizing techniques for the 70 nm process technology demonstrate the tradeoffs that can be achieved with this approach.

Gate sizing to radiation harden combinational logic

Abstract: A gate-level radiation hardening technique for cost-effective reduction of the soft error failure rate in combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve cost-effective tradeoffs between overhead and soft error failure rate reduction. The asymmetry in the logical masking probabilities at a gate is leveraged by decoupling the physical from the logical (Boolean) aspects of soft error susceptibility of the gate. Gates are hardened to single-event upsets (SEUs) with specified worst case characteristics in increasing order of their logical masking probability, thereby maximizing the reduction in the soft error failure rate for specified overhead costs (area, power, and delay). Gate sizing for radiation hardening uses a novel gate (transistor) sizing technique that is both efficient and accurate. A full set of experimental results for process technologies ranging from 180 to 70 nm demonstrates the cost-effective tradeoffs that can be achieved. On average, the proposed technique has a radiation hardening overhead of 38.3%, 27.1%, and 3.8% in area, power, and delay for worst case SEUs across the four process technologies.

Single Event Transients in Digital CMOS—A Review

Abstract: The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore's Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a review of the state-of-the-art in SET testing and modelling, a discussion of mitigation techniques, and a discussion of the impact of technology scaling trends on future SET significance.

FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs

Abstract: This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliability of commercial electronics. For the first time, a fast and accurate methodology FASER based on static, vector-less analysis of error rates due to single event upsets in general combinational circuits is proposed. Accurate models are based on STA-like pre-characterization methods, and logical masking is computed via binary decision diagrams with circuit partitioning. Experimental results indicate that FASER achieves good accuracy compared to the SPICE-based simulation method. The average error across the benchmark circuits is 12% at over 90,000X speed-up. The accuracy can be further improved by more accurate cell library characterization. The run-time for ISCAS '85 benchmark circuits ranges from 10 to 120 minutes. The estimated bit error rate (BER) for the ISCAS'85 benchmark circuits implemented in the 100nm CMOS technology is about 10/sup -5/ FIT.

Single Event Upset: An Embedded Tutorial

Abstract: With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends such as transistor down-sizing, use of new materials, and system on chip architectures continue to increase the sensitivity of systems to soft errors. These errors are random and not related to permanent hardware faults. Their causes may be internal (e.g., interconnect coupling) or external (e.g., cosmic radiation). To meet the system reliability requirements it is necessary for both the circuit designers and test engineers to get the basic knowledge of the soft errors. We present a tutorial study of the radiation-induced single event upset phenomenon caused by external radiation, which is a major source of soft errors. We summarize basic radiation mechanisms and the resulting soft errors in silicon. Soft error mitigation techniques with time and space redundancy are illustrated. An industrial design example, the IBM z990 system, shows how the industry is dealing with soft errors these days.