R. Ahola

Bio: R. Ahola is an academic researcher from Helsinki University of Technology. The author has contributed to research in topics: Phase-locked loop & Frequency synthesizer. The author has an hindex of 6, co-authored 15 publications receiving 170 citations.

A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

Abstract: A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-/spl mu/m CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3/spl deg/ in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes /spl plusmn/2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm/sup 2/. The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.

A single chip CMOS transceiver for 802.11 a/b/g WLANs

Abstract: A 0.18 /spl mu/m dual-band tri-mode CMOS radio, fully compliant with the IEEE 802.11 a/b/g standards, achieves a system noise figure of 5.2/5.6 dB (high gain), and an EVM of 2.7/3.0% for the 2.4/5 GHz bands, respectively. Die area is 12 mm/sup 2/, and power consumption is 200 mW in RX and 240 mW in TX using a 1.8 V supply.

A novel phase detector with no dead zone and a chargepump with very wide output voltage range

Abstract: This paper discusses the effects of the so-called dead zone in the phase detector on the phase-noise behavior of phase-locked loop frequency synthesizers. A novel phase detector that completely overcomes the dead zone problem is introduced. Also, a chargepump with a very wide output voltage range is presented. This chargepump allows the use of a VCO with a wider tuning range and, thus, also a lower noise sensitivity. Measurement results that verify the proper operation of these blocks are also presented.

A phase detector with no dead zone and a very wide output voltage range chargepump

Abstract: This paper discusses the effects of the so-called dead zone in the phase detector on the phase-noise behavior of phase-locked loop frequency synthesizers. A novel phase detector that completely overcomes the dead zone problem is introduced. Also, a chargepump with a very wide output voltage range is presented. This chargepump allows the use of a VCO with a wider tuning range and, thus, also a lower noise sensitivity. Measurement results that verify the proper operation of these blocks are also presented.

Integrated radio frequency synthetizers for wireless applications

Abstract: This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.

Programmable radio transceiver

Abstract: A fully integrated, programmable mixed-signal transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC does not use spiral inductors and instead includes transmission line inductors allowing for improved scalability. Components of the transceiver are programmable to allow the transceiver to switch between different frequency bands of operating. Frequency switching can be accomplished though the content of digital registers coupled to the components.

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

Transceiver architecture selection: Review, state-of-the-art survey and case study

Abstract: © P H O T O D IS C A N D C R E A TA S Feature

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

Abstract: A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Abstract: 1. Introduction. 2. Low Voltage Issues. 3. Sample-and-Hold Operation. 4. A/D Converters. 5. S/H Circuit Architectures. 6. Sampling with a MOS Transistor Switch. 7. Operational Amplifiers. 8. Clock Generation. 9. Double-Sampling. 10. Switched OpAmp Technique. 11. Other Low-Voltage Techniques. 12. Prototypes and Experimental Results. 13. Conclusions. Appendices: Derivation of OTA GBW Requirement. Optimum Input Capacitance. Saturation Voltage.