High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators' structures shows the proposed class-F exhibits the lowest phase noise at the same tank's quality factor and supply voltage. The prototype of the class-F oscillator is implemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of -136 dBc/Hz at 3 MHz offset from the carrier over 5.9-7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm2 while drawing 12 mA from 1.25 V supply.

/pdf/a-class-f-cmos-oscillator-2yqvgodo2p.pdf

A Class-F CMOS Oscillator

A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 μs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.

https://researchrepository.ucd.ie/bitstream/10197/8627/1/2014-05_jssc_w-wu_mm-wave_tx_adpll.pdf

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

To develop the high-performance filters and duplexers required for recent long-term evolution frequency bands in mobile handsets, a surface acoustic wave (SAW) resonator is needed that has a higher quality (Q) and a lower temperature coefficient of frequency (TCF). To achieve this, the authors focused on acoustic energy confinement in the depth direction for a rotated Y-X LiTaO3 (LT) substrate. Characteristics of multilayered substrates with low-impedance and high-impedance layers under LT layer were studied numerically in terms of acoustic energy distribution, phase velocity, coupling coefficient, and temperature characteristics employing a finite-element method simulation. After several calculations, a novel multilayered structure was developed that uses SiO2 for a low-impedance layer and AlN for a high-impedance layer under the thin LT layer. A one-port resonator using the new substrate was fabricated, and its experimental results showed that the developed resonator had a Bode-Q over 4000 and TCF of −8 ppm/°C, which are four times higher than and one-fifth as small as those of a conventional 4° YX-LT SAW resonator, respectively. By applying this technology, a band 25 duplexer with very narrow duplex gap was successfully developed, which shows extremely low insertion loss, steep cutoff characteristics, and stable temperature characteristics.

High-Performance SAW Resonator on New Multilayered Substrate Using LiTaO 3 Crystal

This paper presents two class-C CMOS VCOs with a dynamic bias of the core transistors, which maximizes the oscillation amplitude without compromising the robustness of the oscillation start-up, thereby breaking the most severe trade-off in the original class-C topology. An analysis of several different oscillators, starting with the common class-B architecture and arriving to the proposed class-C design, shows that the latter exhibits a figure-of-merit (FoM) that is closest to the ideal FoM allowed by the integration technology. The class-C VCOs have been implemented in a 90 nm CMOS process with a thick top metal layer. They are tunable between 3.4 GHz and 4.5 GHz, covering a tuning range of 28%. Drawing 5.5 mA from 1.2 V, the phase noise is lower than -152 dBc/Hz at a 20 MHz offset from a 4 GHz carrier. The resulting FoM is 191 dBc/Hz, and varies less than 1 dB across the tuning range.

Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs

This paper discloses a mixed-signal control unit of a fully integrated semiconductor quantum processor SoC realized in a 22nm FD-SOI technology. Independent high-resolution DACs that set the amplitude and pulse-width of the control signals were integrated for each qubit, enabling both a programmable semiconductor qubit operation and a per-qubit individual calibration that compensates for the process variability. The lower deco-herence time of the semiconductor charge-qubits as compared to their spin-qubit counterparts was mitigated by using a high frequency of control unit operation. This is facilitated by the co-integration on the same die of the semiconductor quantum structures together with their corresponding classic control circuitry. The main challenge of achieving deep cryogenic operation for the mixed-signal classic control circuit was surpassed by using programmable local heating DACs that slightly boost the local temperature of the control blocks above the average temperature of the die, which needs to be maintained around 4 K to enable a reliable quantum operation. A staged multi-phase operation was adopted for the digital core in order to minimize the quantum decoherence originated in digital noise injection. The high-frequency clock tree and divider allows the generation of sub-20 ps fast edge control pulses with programmable widths down to 166 ps. This offers a wide quantum computation window when compared with the 1µs decoherence time of the charge-qubit structures.

A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip

Base-station (BTS) RX oscillator phase noise requirements between 600kHz and 3MHz are difficult to satisfy using a fully monolithic VCO fabricated in bulk-CMOS technology. The GSM-900-BTS and the DCS-1800-BTS RX specifications at 800kHz of −147dBc/Hz and −138dBc/Hz, respectively, are considered the most difficult to meet. In GSM mobile stations (MS), the transmit and receive bands are 20MHz apart, which sets a stringent TX phase noise requirement of −162dBc/Hz at 20MHz offset [1]. A VCO satisfying this inadvertently meets the relatively relaxed RX specification.

A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations

Growing demands for higher data rates and the sheer volume of data traffic have been the main drivers for the evolution of Third-Generation Partnership Project (3GPP) cellular communication standards. Increased data rates have, in turn, enabled network operators to offer consumers unparalleled performance and a seamless user experience (UX). To address future demands for even better performance, the UX has to evolve to support various new high-speed packet access (HSPA) configurations, such as dual-cell high-speed downlink (DL) packet access (DC-HSDPA), DC-HSDPA together with dual-band or multiple-input, multiple-output (MIMO), DC high-speed uplink (UL) packet access (DC-HSUPA), high-speed DL packet access (HSDPA) with MIMO, and long-term evolution (LTE) with carrier aggregation (CA).

Cost-Efficient, High-Volume Transmission: Advanced Transmission Design and Architecture of Next Generation RF Modems and Front-Ends

We present a 60-GHz FMCW radar transmitter based on an all-digital phase-locked loop (ADPLL) with ultra-wide linear frequency modulation. Multirate, two-point modulation generates an ultra-linear programmable frequency ramp. A novel, closed-loop DCO gain linearization method employing 24kb of SRAM realizes a GHz-level triangular chirp with high sweep linearity, and enables hitless modulation through multiple DCO tuning banks. Measured frequency error (i.e., nonlinearity) in the FMCW ramp is only 117-kHzrms for a 62-GHz carrier with 1.22-GHz bandwidth. The synthesizer is transformercoupled to a 3-stage neutralized power amplifier that delivers +5 dBm to a 50-Ω load. Implemented in 65-nm CMOS, the transmitter prototype consumes 89 mW from a 1.2-V supply.

A mm-Wave FMCW radar transmitter based on a multirate ADPLL

This letter presents a single-electron injection device for position-based charge qubit structures implemented in 22-nm fully depleted silicon-on-insulator CMOS. Quantum dots are implemented in local well areas separated by tunnel barriers controlled by gate terminals overlapping with a thin 5-nm undoped silicon film. Interface of the quantum structure with classical electronic circuitry is provided with single-electron transistors that feature doped wells on the classic side. A small $0.7\times 0.4\,\,\mu \text{m}^{2}$ elementary quantum core is co-located with control circuitry inside the quantum operation cell which is operating at 3.5 K and a 2-GHz clock frequency. With this apparatus, we demonstrate a single-electron injection into a quantum dot.

/pdf/a-single-electron-injection-device-for-cmos-charge-qubits-56vgt29eva.pdf

R. Bogdan Staszewski

Papers

A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip

A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations

Cost-Efficient, High-Volume Transmission: Advanced Transmission Design and Architecture of Next Generation RF Modems and Front-Ends

A mm-Wave FMCW radar transmitter based on a multirate ADPLL

A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22-nm FD-SOI