R. Hasumi

Bio: R. Hasumi is an academic researcher from Toshiba. The author has contributed to research in topics: Schottky diode & Process window. The author has an hindex of 2, co-authored 2 publications receiving 116 citations.

Comprehensive Study on Injection Velocity Enhancement in Dopant-Segregated Schottky MOSFETs

Abstract: The carrier transport in dopant-segregated Schottky (DSS) and conventional MOSFETs was thoroughly investigated in terms of carrier injection velocity, vinj. It was found that vinj enhancement associated with the velocity overshoot enhances the current drivability in DSS, in addition to the reduction of parasitic resistance. A physical-based model was newly developed to explain the velocity overshoot behavior and reproduced the experimental data very well. Moreover, a novel type of DSS FinFET to take full advantage of the velocity overshoot was proposed and demonstrated as a primary study.

Scaling of 32nm low power SRAM with high-K metal gate

Abstract: This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG Tinv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum2 cell to meet low power application requirements.

System comprising a semiconductor device and structure

Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Semiconductor device and structure

Abstract: A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Method for fabrication of a semiconductor device and structure

Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Process Technology Variation

Abstract: Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

3D semiconductor device and structure

Abstract: An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.