Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits.

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Adaptive Debug and Diagnosis without Fault Dictionaries

Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach is named POINTER for `Partially Overlapping Impact couNTER' and combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits. In addition, even without additional patterns this analysis method provides good resolution for volume diagnosis, too.

Adaptive Debug and Diagnosis Without Fault Dictionaries

To cope with the numerous defect mechanisms in nanoelectronic technology, more and more complex fault models have been introduced. Each model comes with its own properties and algorithms for test generation and logic diagnosis. In diagnosis, however, the defect mechanisms of a failing device are not known in advance, and algorithms that assume a specific fault model may fail. Therefore, diagnosis techniques have been proposed that relax fault assumptions or even work without any fault model. In this chapter, we establish a generalized fault modeling technique and notation. Based on this notation, we describe and classify existing models and investigate the properties of a fault model independent diagnosis technique.

Generalized Fault Modeling for Logic Diagnosis

Design, verification and test of integrated circuits with millions of gates put strong requirements on design time, test volume, test application time, test speed and diagnostic resolution. In this paper, an overview is given on the common aspects of these tasks and how they interact. Diagnosis techniques may be used after manufacturing, for chip characterization and field return analysis, and even for rapid prototyping.

Some common aspects of design validation, debug and diagnosis

Automated test generation for digital systems encompasses three activities: selecting a description method, developing a fault model and generating tests to detect the faults covered by the fault model. The efficiency of test generation (quality, speed) is highly depending on the description method and fault models. As the complexity of digital systems continues to increase, the gate level test generation methods have become obsolete. Promising approaches are high-level methods. In this paper, a method for describing microprocessors as a special case of digital systems is explained and modeling faults with High-Level Decision Diagrams (HLDD) is presented. HLDDs serve as a basis for a general theory of test generation for mixed-level representations of systems, similarly as we have Boolean algebra for logic-level. HLDDs can be used for representing systems uniformly either at logic-level, high- level or simultaneously at both levels. The fault model on HLDDs represents a generalization of the classical gate- level stuck-at fault model to higher levels - the latter was defined for Boolean expressions whereas the former is defined for nodes in HLDDs having more general interpretation.

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Modeling Microprocessor Faults on High-Level Decision Diagrams

Design verification is taking an increasing proportion of the design cycle of system-on-chip (SoC) designs. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems based in 2004 IC/ASIC Functional Verification Study (2005). Running regression suites against the design can take up to several years of CPU time to complete. In this paper we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system level verification. As shown in various hardware/software co-verification tools as stated in R. Klein (1996) and M. Stanbro (1998), the overall load on a simulation can be reduced by eliminating code and data references from the set of bus cycles generated by the processor model. These same techniques can be applied by hardware designers and verification engineers to use firmware, hardware diagnostics, and other software as a basis for creating functional verification tests. This software is often available from prior versions of the design or other groups on the design team. Simulation run-times can be reduced by partitioning the processor's memory space between the logic simulation and the processor model.

R. Klein

Papers

Accelerating functional simulation for processor based designs