R.R. Harrison

Bio: R.R. Harrison is an academic researcher from University of Utah. The author has contributed to research in topics: Amplifier & Bioamplifier. The author has an hindex of 2, co-authored 2 publications receiving 1482 citations.

A low-power low-noise CMOS amplifier for neural recording applications

Abstract: There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

A floating gate common mode feedback circuit for low noise amplifiers

Abstract: Most low noise amplifier designs focus on eliminating sources of noise that are intrinsic to the amplifier (thermal noise, I If noise). As integrated circuit design moves increasingly towards mixed signal implementations, the design of low-noise analog amplifiers must be re-evaluated to consider the switching noise generated by on-chip digital circuitry. We designed three fully differential versions of a previously reported single-ended low-noise amplifier for biomedical applications. Each design uses a different common mode feedback (CMFB) circuit. The first uses a standard continuous-time CMFB circuit, the second uses a switched capacitor CMFB circuit, and the third uses a novel floating gate CMFB circuit. A test chip has been fabricated in a 1.5 /spl mu/m CMOS process. The fully differential amplifiers outperform the single-ended amplifier in the presence of switching noise. The amplifier with the floating gate CMFB circuit has the lowest total harmonic distortion over the critical range and exhibits the smallest fluctuation in the common mode output level.

A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System

Abstract: Recent work in field of neuroprosthetics has demonstrated that by observing the simultaneous activity of many neurons in specific regions of the brain, it is possible to produce control signals that allow animals or humans to drive cursors or prosthetic limbs directly through thoughts. As neuroprosthetic devices transition from experimental to clinical use, there is a need for fully-implantable amplification and telemetry electronics in close proximity to the recording sites. To address these needs, we developed a prototype integrated circuit for wireless neural recording from a 100-channel microelectrode array. The design of both the system-level architecture and the individual circuits were driven by severe power constraints for small implantable devices; chronically heating tissue by only a few degrees Celsius leads to cell death. Due to the high data rate produced by 100 neural signals, the system must perform data reduction as well. We use a combination of a low-power ADC and an array of "spike detectors" to reduce the transmitted data rate while preserving critical information. The complete system receives power and commands (at 6.5 kb/s) wirelessly over a 2.64-MHz inductive link and transmits neural data back at a data rate of 330 kb/s using a fully-integrated 433-MHz FSK transmitter. The 4.7times5.9 mm2 chip was fabricated in a 0.5-mum 3M2P CMOS process and consumes 13.5 mW of power. While cross-chip interference limits performance in single-chip operation, a two-chip system was used to record neural signals from a Utah Electrode Array in cat cortex and transmit the digitized signals wirelessly to a receiver

System and method for waking an implantable medical device from a sleep state

Abstract: A system and method for waking up a satellite implantable medical device ('IMD') from a sleep state in which power consumption by the satellite IMD is essentially zero. The satellite IMD may be adapted to perform one or more designated measurement and/or therapeutic functions. The satellite IMD includes a wake-up sensor that is adapted to sense the presence or absence of a wake-up field generated by a primary IMD or an external device. The wake-up field may be an electromagnetic field, a magnetic field, or a physiologically sub-threshold excitation current (i.e., E-field). Upon sensing by the wake-up sensor of the wake-up field, other components of the satellite IMD, which may include a controller, a sensing and/or therapy module, and/or a communications module, are awakened to perform one or more designated functions.

A low-power, low-noise CMOS amplifier for neural recording applications

Abstract: There is a need among scientists and clinicians for low-noise, low-power biosignal amplifiers capable of amplifying signals in the mHz to kHz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully-implantable multielectrode arrays has created the need for fully-integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudo-resistor to amplify signals down to the mHz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches that limit. The resulting amplifier, built in a standard 1.5/spl mu/m CMOS process, passes signals from 0.1mHz to 7.2kHz with an input-referred noise of 2.2/spl mu/Vrms and a power dissipation of 80/spl mu/W while consuming 0.16mm/sup 2/ of chip area.

An Energy-Efficient Micropower Neural Recording Amplifier

Abstract: This paper describes an ultralow-power neural recording amplifier. The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date. We describe low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage. Since neural amplifiers must include differential input pairs in practice to allow robust rejection of common-mode and power supply noise, our design appears to be near the optimum allowed by theory. The bandwidth of the amplifier can be adjusted for recording either neural spikes or local field potentials (LFPs). When configured for recording neural spikes, the amplifier yielded a midband gain of 40.8 dB and a -3-dB bandwidth from 45 Hz to 5.32 kHz; the amplifier's input-referred noise was measured to be 3.06 muVrms while consuming 7.56 muW of power from a 2.8-V supply corresponding to a noise efficiency factor (NEF) of 2.67 with the theoretical limit being 2.02. When configured for recording LFPs, the amplifier achieved a midband gain of 40.9 dB and a -3-dB bandwidth from 392 mHz to 295 Hz; the input-referred noise was 1.66 muVrms while consuming 2.08 muW from a 2.8-V supply corresponding to an NEF of 3.21. The amplifier was fabricated in AMI's 0.5-mum CMOS process and occupies 0.16 mm2 of chip area. We obtained successful recordings of action potentials from the robust nucleus of the arcopallium (RA) of an anesthesized zebra finch brain with the amplifier. Our experimental measurements of the amplifier's performance including its noise were in good accord with theory and circuit simulations.

A 2 $\mu\hbox{W}$ 100 nV/rtHz Chopper-Stabilized Instrumentation Amplifier for Chronic Measurement of Neural Field Potentials

Abstract: This paper describes a prototype micropower instrumentation amplifier intended for chronic sensing of neural field potentials (NFPs). NFPs represent the ensemble activity of thousands of neurons and code-useful information for both normal activity and disease states. NFPs are small - of the order of tens of muV- and reside at low bandwidths that make them susceptible to excess noise. Therefore, to ensure the highest fidelity of signal measurement for diagnostic analysis, the amplifier is chopper-stabilized to eliminate 1/f and popcorn noise. The circuit was prototyped in an 0.8 mum CMOS process and consumes under 2.0 muW from a 1.8 V supply. A noise floor of 0.98 muVrms was achieved over a bandwidth from 0.05 to 100 Hz; the noise-efficiency factor of 4.6 is one of the lowest published to date. A flexible on-chip high-pass filter is used to suppress front-end electrode offsets while maintaining relevant physiological data. The monolithic architect and micropower low-noise low-supply operation could help enable applications ranging from neuroprosthetics to seizure monitors that require a small form factor and battery operation. Although the focus of this paper is on neurophysiological sensing, the circuit architecture can be applied generally to micropower sensor interfaces that benefit from chopper stabilization.