This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.

Area efficient modified vedic multiplier

This paper mainly describes the design of 8-bit Vedic multiplier and its performance comparison with existing multiplier such as i) Booth multiplier ii) Array multiplier iii) Wallace tree multiplier. Vedic calculations are the olden scheme of mathematics, which has a procedure of mathematical calculations to compute the multiplication of two 8-bit number. In this work Urdhva Tiryagbhyam (vertical and crosswise) Vedic sutra is used for multiplier design which provides better performance and consumes lesser time for computation. The Urdhva Tiryagbhyam is the finest sutra and universal one among additional sutras and which represents the different multiplication process compared to normal multiplication. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is also verified on Spartan-6 Field Programmable Gate Array (FPAGA). Finally, the proposed 8-bit multiplier design is compared with 8-bit Booth multiplier, Array multiplier and Wallace tree multiplier in terms of Area, Memory and Delay. The result shows proposed 8-bit Vedic multiplier is efficient and consumes 14.219ns time for the multiplication process which is better compared to 8-bit, Booth multiplier, Array multiplier and Wallace tree multiplier.

Design of 8 Bit Vedic Multiplier Using Urdhva Tiryagbhyam Sutra With Modified Carry Save Adder

Multiplication is basic function in arithmetic operations. Multiplication based operations such as multiply and Accumulate unit (MAC), convolution, Fast Fourier Transform (FFT), filtering are widely used in signal processing applications. As, multiplication dominates the execution time of DSP systems, there is need to develop high speed multipliers. Ancient Vedic mathematics facilitates the solution to some extent. In this paper, concept of Urdhwa-Tiryagbhyam is used i.e., vertically and crosswise multiplication to implement 16×16 Bit Vedic multiplier and optimization is achieved by using carry save adders. Comparing with previous architectures, proposed architecture achieves 33.26% reduction in combinational path delay. The Vedic multiplier proposed is implemented in VHDL whereas synthesized and simulated using Xilinx ISE Design Suite 14.5.

Design and optimization of 16×16 Bit multiplier using Vedic mathematics

This paper presents the VLSI Architecture for High-Speed 32-bit Multiplier using Vedic Mathematic sutras. Two sutras among 16 sutras of Vedic Mathematics can be applied for multiplication. Nikhilam Sutra and Urdhva-Tiryagbhyam Sutra are used to implement Vedic Multipliers. In this paper, VLSI architecture for both sutras is implemented and synthesized in Xilinx software. The delay and memory for multiplier using Urdhva-Tiryagbhyam sutra are less when compared to multiplier using Nikhilam sutra. Further, the structure of Vedic Multiplier is modified by using Binary to excess-1 code converter so as to obtain less delay for the multiplier. By replacing normal adders with Binary to excess-1 code converter in multipliers we can achieve reduction in delay.

VLSI architecture for delay efficient 32-bit multiplier using vedic mathematic sutras

Multipliers act as processors and take on the notable work of many computing frameworks. The speed of the processor is profoundly affected by the speed of their multipliers. In order to improve the system speed, faster and more efficient multipliers should be used. A Vedic multiplier is one of the best solution that can be used to perform multiplications at a faster rate by eliminating the steps that are not needed in usual multiplication process. Power consumption is another critical issue in embedded systems that cannot be ignored. Reversible logic has become notable in the recent years because of its potential to reduce power utilization, which is a major concern in digital design. In this work, a high-speed 16 × 16 Vedic multiplier was designed using Urdhva Tiryagbhyam (UT) sutra, which is derived from Vedic mathematics. This is a simple structure as well as an unbeatable combination for creating any complex multiplication operations for services where speed is of prime importance. This work also proposes a new method based on Elliptic Curve Cryptography (ECC) system for encryption and decryption using Vedic multiplication. By using Vedic Multiplication in ECC the processing time is perfectly reduced. The proposed Elliptic curve cryptography method is much faster than other elliptic curve cryptographic algorithms. Compared to other cryptographic techniques, the key size required to provide equivalent security is small in ECC.

Performance improvement of elliptic curve cryptography system using low power, high speed 16 × 16 Vedic multiplier based on reversible logic

This paper briefly describes the Urdhva-Tiryagbhyam Sutra of vedic mathematics and we have designed multiplier based on the sutra. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras which are discovered by Sri Bharti Krishna Tirthaji. In this era of digitalization, it is required to increase the speed of the digital circuits while reducing the on chip area and memory consumption. In various applications of digital signal processing, multiplication is one of the key component. Vedic technique eliminates the unwanted multiplication steps thus reducing the propagation delay in processor and hence reducing the hardware complexity in terms of area and memory requirement. We implement the basic building block: 16 × 16 Vedic multiplier based on Urdhva-Tiryagbhyam Sutra. This Vedic multiplier is coded in VHDL and synthesized and simulated by using Xilinx ISE 10.1. Further the design of array multiplier in VHDL is compared with proposed multiplier in terms of speed and memory.

R.S. Sisal

Papers

Design and implementation of 16 × 16 multiplier using Vedic mathematics