R. Sanjay

Bio: R. Sanjay is an academic researcher from National Institute of Technology, Tiruchirappalli. The author has contributed to research in topics: Amplifier & Cascode. The author has an hindex of 4, co-authored 7 publications receiving 30 citations.

A low-power low-noise and high swing biopotential amplifier in 0.18 µm CMOS

Abstract: In this paper, a low-power, low-noise and high swing capacitively coupled instrumentation amplifier for biomedical applications is proposed. It uses the folded cascode operational transconductance amplifier (FC-OTA) with current scaling at the output branch to reduce the noise. To overcome the reduction in the effective transconductance of the OTA due to current scaling, series–series and shunt–shunt feedback techniques are proposed at the folded node of the FC-OTA and the composite transistor is proposed at the bottom current source of the FC-OTA. An optimization procedure is also proposed for sizing the input transistors of the FC-OTA to obtain better noise-power tradeoff. To assess the efficacy of these techniques, a biopotential amplifier is designed in 0.18 µm CMOS process and it is studied through simulation. From this study, it is found that the proposed amplifier has a 1.5–22 times and 1.4 times higher input swing and output swing respectively compared to those reported in literature. It has a gain of 39.75 dB, a bandwidth of 0.3 Hz–4.4 kHz and a total input-referred noise of 3.19 µVrms integrated over 1 Hz–10 kHz. The power consumption of the amplifier is 4.07 µW at a VDD of 1.8 V. It achieves a noise efficiency factor of 2.78, and provides input and output signal swings of 14.86 mVpp, and 1.38 Vpp respectively at THD of 1%.

A PVT compensated nano-ampere current reference in 0.18 µm CMOS

Abstract: A PVT compensated sub-µA current reference is proposed in this paper. It is based on the summation of a proportional to absolute temperature (PTAT) current with a complementary to absolute temperature current. The current generators are realized using the subthreshold beta multipliers. The PTAT current generator of the proposed current reference behaves always as PTAT independent of transistor sizing. The process compensation technique is based on the concept of an inverse process dependency between $$\beta \left( { = \mu C_{OX} {W \mathord{\left/ {\vphantom {W L}} \right. \kern-0pt} L}} \right)$$β=μCOXW/L and the threshold voltage $$V_{TH}$$VTH of the MOS transistor at any process corner. A current reference of 100 nA is implemented in CMOS 0.18 µm technology and studied through simulation. The proposed circuit has a temperature coefficient of 335 ppm/°C in the temperature range of 0---100 °C. It provides a low process variation ofý?ý2.1% and a lower line sensitivity of 0.093%/V in the supply voltage range of 1.35---3 V. It achieves a better figure of merit of 5.487% compared to the current references reported in the literature.

High-gain inductorless Wideband Balun-LNA using asymmetric CCC & BIST using RMS detectors

Abstract: In this paper, an inductorless wideband balun-low noise amplifier (LNA) using current source loads, common-mode feedback (CMFB), asymmetric capacitive cross-coupling (CCC) and auxiliary common-source amplifier are proposed to obtain low noise figure (NF) and high gain. The asymmetric CCC boosts the gain and reduces the NF. The CMFB fixes the output to a common mode voltage. RMS detectors are proposed to realize a low-cost built-in self-test (BIST) circuit for measuring the gain of the LNA during its entire lifespan. The proposed balun-LNA is implemented in 0.18 µm CMOS process technology and the performance is studied through post-layout simulations. PVT and Monte Carlo simulations are performed to check for the robustness and yield of the circuit. From these analyses, it is found that the integrated average gain of the LNA obtained with and without the RMS detectors is 19.1 dB and 20.1 dB respectively in the 3 dB-band of 0.18–2 GHz. NF of the LNA in this band is 2.87 dB. The average IIP3, IIP2, and 1 dB compression points of the LNA are (−4.89 dBm, +28.57 dBm, −20.42 dBm) respectively. The proposed LNA dissipates a power of 4.9 mW with a supply of 1.2 V and requires an area of 0.04 mm2.

Design Of Analog Cmos Integrated Circuits

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0.5 V Differential Difference Transconductance Amplifier and Its Application in Voltage-Mode Universal Filter

Abstract: This paper presents an innovative CMOS structure for Differential Difference Transconductance Amplifiers (DDTA). While the circuit operates under extremely low voltage supply 0.5 V, the circuit’s performance is improved thanks to using the multiple-input MOS transistor (MI-MOST), the bulk-driven, self-cascode and partial positive feedback (PPF) techniques. As a result, the DDTA structure is less complex, with high gain of 93 dB, wide input voltage range nearly rail-to-rail, and wide transconductance tunability. As an example of application, a second-order voltage-mode universal filter using three DDTAs and two 6 pF integrated capacitors is presented. The filter is designed such that no matching conditions are required for the input and passive components, and the input signals need not be inverted. The natural frequency and the quality factor can be set orthogonally while the natural frequency can be electronically controlled. The circuit was designed and simulated in Cadence environment using $0.18 \mu \text{m}$ TSMC technology. The simulation results including intensive Monte-Carlo (MC) and process, temperature, voltage (PVT) analysis confirm the stability and the robustness of the design to process, mismatch variation and PVT corners.