We evaluate the impact of band-to-band tunneling (BTBT) on the characteristics of n-channel junctionless transistors (JLTs) A JLT that has a heavily doped channel, which is fully depleted in the off state, results in a significant band overlap between the channel and drain regions This overlap leads to a large BTBT of electrons from the channel to the drain in n-channel JLTs This BTBT leads to a nonnegligible increase in the off-state leakage current, which needs to be understood and alleviated In the case of n-channel JLTs, tunneling of electrons from the valence band of the channel to the conduction band of the drain leaves behind holes in the channel, which would raise the channel potential This triggers a parasitic bipolar junction transistor formed by the source, channel, and drain regions induced in a JLT in the off state Tunneling current is observed to be a strong function of the silicon body thickness and doping of a JLT We present guidelines to optimize the device for high on-to-off current ratio Finally, we compare the off-state leakage of bulk JLTs with that of silicon-on-insulator JLTs

Effect of Band-to-Band Tunneling on Junctionless Transistors

Extremely thin-film SOI MOSFET's with silicon film thickness down to 8 nm have been fabricated without inducing serious source/drain series resistance by employing a gate recessed structure. The influence of extremely thin silicon film on the electron mobility has been experimentally studied. The results show an abrupt mobility decrease in the device with less than 10 nm silicon film thickness. The measured mobility versus effective field below 10 nm silicon film thickness shows that a different scattering mechanism is involved in carrier conduction in 10 nm t/sub si/ region. The reasons for the mobility decrease have been examined from a device simulation and measurements. >

Electron mobility behavior in extremely thin SOI MOSFET's

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E/sub m/). Experimental results using SOI MOSFET's with body contacts indicate that E/sub m/ is just a weak function of thin-film SOI thickness (T/sub si/ and that E/sub m/ can be significantly lower than in a bulk device with drain junction depth (X/sub j/) comparable to SOI's T/sub si/. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I/sub G/) of studying E/sub m/ in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought. >

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

We present a physics-based compact model for two-dimensional (2D) field-effect transistors (FETs) based on monolayer semiconductors such as MoS2 A semi-classical transport approach is appropriate for the 2D channel, enabling simplified analytical expressions for the drain current In addition to intrinsic FET behavior, the model includes contact resistance, traps and impurities, quantum capacitance, fringing fields, high-field velocity saturation, and self-heating, the latter being found to play an important role The model is calibrated with state-of-the-art experimental data for n- and p-type 2D-FETs, and it can be used to analyze device properties for sub-100 nm gate lengths Using the experimental fit, we demonstrate the feasibility of circuit simulations using properly scaled devices The complete model is implemented in SPICE-compatible Verilog-A, and a downloadable version is freely available at the nanoHUBorg

S2DS: Physics-based compact model for circuit simulation of two-dimensional semiconductor devices including non-idealities

Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.

Dynamic flash memory cells with ultra thin tunnel oxides

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of +or-150 AA was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed. >

Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers

The bias dependence of the drain current noise power of SOI (silicon-on-insulator) MOSFETs was studied, and low frequency noise overshoot at the drain current was observed. The overshoot has a width of about 0.7 V and exhibits a peak noise power which is two orders of magnitude higher than the normal noise level. The SOI devices used in this study were N-channel polysilicon gate MOSFETs on SIMOX (separation by implantation of oxygen) wafers fabricated with conventional submicron CMOS technology. The SOI film thickness, the buried-oxide thickness, and the gate oxide are 100 nm, 300 nm, and 11.5 nm, respectively. A computer-controlled test system was used to conduct the I-V and noise measurement automatically. A model explaining the occurrence of the noise overshoot and the noise peak is proposed. >

Noise overshoot at drain current kink in SOI MOSFET

A quantitative model which relates the SOI (silicon-on-insulator) MOSFET breakdown voltage to key parameters such as channel length, SOI film thickness, and gate voltage is presented The SOI breakdown is caused by electron impact ionization current produced near the drain which is subsequently amplified by a parasitic lateral bipolar transition This model is based on analytic modeling, quasi-2-D simulation and experimental study of the maximum drain electric field in SOI, and a novel method for measuring the lateral BJT (bipolar junction transistor) current gain beta using GIDL (gate-induced drain leakage) current It can accurately model the breakdown voltage within 02 V for different channel lengths, gate voltages, and SOI film thicknesses >

An accurate model of thin film SOI-MOSFET breakdown voltage

I/sub G/ in P-channel SOI (silicon-on-insulator) MOSFETs is modeled and device degradation is characterized. It is found that E/sub m/ is about the same as in bulk devices. The SOI devices used in this study were p/sup +/ polysilicon gate P-channel MOSFETs fabricated using a modified submicron CMOS technology on SIMOX (Separation by IMplanted OXygen) wafers. It is shown that the peak degradation of both I/sub D/ and G/sub m/ occurs close to the I/sub g/ peak. This indicates that electron injection is the dominant mechanism for PMOS degradation in SOI and similar to bulk PMOS. >

Hot electron gate current and degradation in P-channel SOI MOSFETs

The trap density of both front and back interfaces of SOI (silicon-on-insulator) devices is estimated using low frequency noise measurement. The authors present the complete set of effective mobilities for both n- and p-channel SOI MOSFETs at both the front and back channels and relate them to the trap densities. It is found that the interface qualities of the front and back sides are similar in SIMOX (separation by implanted oxygen) SOI MOSFETs from the noise and mobility standpoint. The very low field effective mobility of SOI NMOS is lower than that of bulk NMOS due to increased interface trap densities for SOI devices and the effective mobility of the edge transistor is lower. >

R. Solomon

Papers

Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers

Noise overshoot at drain current kink in SOI MOSFET

An accurate model of thin film SOI-MOSFET breakdown voltage

Hot electron gate current and degradation in P-channel SOI MOSFETs

Interface quality of SOI MOSFET's reflected in noise and mobility