Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

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Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Self-heating is an important issue for SOI CMOS, and hence, so is its characterization and modeling. This paper sets out how the critical parameters for modeling, i.e., thermal resistance and thermal time-constants, may be obtained using purely electrical measurements on standard MOS devices. A summary of the circuit level issues is presented, and the physical effects contributing to thermally related MOSFET behavior are discussed. A new thermal extraction technique is presented, based on an analytically derived expression for the electro-thermal drain conductance in saturation. Uniquely, standard MOSFET structures can be used, eliminating errors due to additional heat flow through special layouts. The conductance technique is tested experimentally and results are shown to be in excellent agreement with thermal resistance values obtained from noise thermometry and gate resistance measurements using identical devices. It is demonstrated that the conductance technique can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.

Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques

We report the first measurements on deep submicron strained-Si n-MOSFETs. In spite of the high channel doping and vertical effective fields, electron mobility is enhanced by /spl sim/75% compared to typical MOSFET mobilities. The extrinsic transconductance is increased by /spl sim/45% for channel lengths of 0.1 /spl mu/m, when AC measurements are used to reduce self-heating effects. The improved transconductance demonstrates the use of strain-induced enhancements in both mobility and high-field transport to increase the average electron velocity, while maintaining the channel doping required to suppress short channel effects.

Transconductance enhancement in deep submicron strained Si n-MOSFETs

The buried-oxide in SOI MOSFET inhibits heat dissipation in the Si film and leads to increase in transistor temperature. This paper reports a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs. The AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance (R/sub th/) and thermal capacitance (C/sub th/) associated with the SOI device. This methodology is important to remove the misleadingly large self-heating effect from the DC I-V data in device modeling. Not correcting for SHE may lead to significant error in circuit simulation. After SHE is accounted for, the frequency-dependent SHE may be disabled in circuit simulation without sacrificing the accuracy, thus providing faster circuit simulation for high-frequency circuits.

SOI thermal impedance extraction methodology and its significance for circuit simulation

In this paper, we present a new technique for isolating the electrical behavior of an SOI MOSFET's from the self-heating effect using an AC conductance method. This method reconstructs an I-V curve by integrating high frequency output conductance data. The heating effect is eliminated when the frequency is much higher than the inverse of the thermal time constant of the SOI device. We present measurement results from SOI MOSFET's that demonstrate that heating can indeed be significant in SOI devices. >

An AC conductance technique for measuring self-heating in SOI MOSFET's

We report a frequency-dependent output conductance of partially depleted SOI MOSFETs. For high-frequency analog applications, the output conductance is less than half and the dynamic range of V/sub d/ is two times higher than the dc I-V characteristics would indicate. A simple physical model for the phenomenon that involves a phenomenological body charging capacitance and can fit data within 10% is presented.

AC output conductance of SOI MOSFETs and impact on analog applications

This work presents a comparative study of advanced MOSFET structures that have been proposed for around 0.1 /spl mu/m generation in the subjects of short-channel effect, drain saturation current, and relative gate delay. Our approach differs from other studies in that we emphasize compact analytical models and parametric comparison. These heuristic and analytic models are guided by experimental and simulational data. Based on these models, key device design parameters are extracted and compared. This approach provides good insight for device design, quick figure-of-merit, and a framework for analyzing a wide variety of MOSFETs. The devices in this study are : (a) uniformly-doped MOSFET, (b) delta-doped MOSFET, (c) pocket-implanted MOSFET, (d) SOI MOSFET, and (e) double-gated MOSFET. Their generic extensions cover almost every advanced MOSFET.

R. Tu

Papers

An AC conductance technique for measuring self-heating in SOI MOSFET's

AC output conductance of SOI MOSFETs and impact on analog applications

A comparative study of advanced MOSFET structures