Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

Field Programmable Gate Array Applications—A Scientometric Review

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

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A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

The rapid development in wireless networking has been witnessed in past several years, which aimed on high speed and long range applications. The increasing demand for low data and low power networking led to the development of ZigBee technology. This technology was developed for Wireless Personal Area Networks (WPAN), directed at control and military applications, where low cost, low data rate, and more battery life were main requirements. ZigBee is a standard, which defines set of communication protocols. ZigBee based devices operate in 868 MHz, 915 MHz and 2.4 GHz frequency bands. It has maximum data rate of 250K bits per second. This paper explores the architectural blocks of digital ZigBee transmitter. The advancement in VLSI technology led to the development of more efficient, accurate, small, and fast design. ZigBee has potential application in Internet of Things (IoT), because of the fact that it is a low power and low data rate device. The main focus of the project is to design a ZigBee transmitter using Verilog for IoT applications. A basic digital ZigBee transmitter consists of cyclic redundancy check, Bit-to-Symbol block, Symbol-to-Chip block, and a Modulator. This paper presents digital design and Verilog-HDL simulation of the Cyclic Redundancy Check and Bit-to-Symbol block of the ZigBee transmitter.

Design and simulation of state-of-art ZigBee transmitter for IoT wireless devices

Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

The increasing industrial demand for low data-rate and low power networking protocols for IoT communications from past several years led to the development of ZigBee technology. As a result of advancement in VLSI technologies, development of more power efficient, accurate, and small digital ZigBee transmitter design has become achievable but yet challenging. This paper presents digital design and FPGA PoC implementation for the 2.4 GHz-band digital ZigBee transmitter. The proposed hardware design of the transmitter described by utilizing Verilog Hardware Description Language and the prototype implementation is done by employing Xilinx Vivado 2016.2. The paper demonstrates the design of the four building blocks of an energy efficient digital ZigBee transmitter; i.e. cyclic redundancy check, bit-to-symbol block, symbol-to-chip block, and offset quadrature phase shift keying Modulator. Simulation waveform verifies functionality of the transmitter and its low power and low data-rate suitability for Internet of Things' applications.

Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications

It is well-known that advanced encryption standard (AES) algorithm is used for protection against various classes of wireless attacks in wireless communication standard such as WiFi, WiMAX, Zigbee and Bluetooth. However, the AES is a complex algorithm that consumes a larger design core, time, and power source. Hence, this paper presents a development of an improved power-throughput Blowfish algorithm on Zynq-7000 field-programmable gate array (FPGA) as an alternative security algorithm. The proposed memory-based method is used to optimize the performance of Blowfish. The performance is analyzed in terms of its architecture, throughput, and power consumption. Results show that the proposed Blowfish reduces slice usage by 63% and increases throughput by 29% at low power consumption.

Development of an improved power-throughput Blowfish algorithm on FPGA

As wireless broadband technology has become very popular, the introduction of Worldwide Interoperability for Microwave Access (WiMAX) based on IEEE 802.16 standard has increased the demand for wireless broadband access in the fixed and the mobile devices. This development makes wireless security a very serious concern. Even though the Advanced Encryption Standard (AES) has been popularly used for protection in WiMAX applications, still WiMAX is exposed to various classes of wireless attack, such as interception, fabrication, modification, and reply attacks. The complexity of AES also produces high power consumption, long processing time, and large memory. Hence, an alternative cryptography algorithm that has a lower power consumption, faster and smaller memory, is studied to replace the existing AES. A Software Defined Radio (SDR) is proposed as a different way of proving the performance of the cryptography algorithm in real environments because it can be reprogrammed, which leads to design cost and time reductions.

A Survey of High Performance Cryptography Algorithms for WiMAX Applications Using SDR

This paper describes implementation of an offset quadrature phase shift keying (OQPSK)-pulse-shaping block as a part of digital transmitter The implementation is based on 24 GHz-band IEEE 802154 standard In this paper, the implementation results are compared to the results of OQPSK modulator and pulse-shaping block in terms of simulation waveform, design size, and synthesis run time These blocks were designed using Verilog code through Xilinx ISE as a new design method and been implemented on Spartan3E XC3S500E field programmable gate array (FPGA) Current review shows that configurations for the implementation of OQPSK-pulse-shaping block, require 264% slices, 229% sliced flip-flops, and 155% look-up tables (LUTs), which is much better than the results of OQPSK modulator and pulse-shaping block At clock frequencies of 2 MHz and 25 MHz, the synthesis run time for OQPSK-pulse-shaping block shows substantial improvement with 48 ns faster than the two blocks

Implementation of IEEE 802.15.4-based OQPSK-pulse-shaping block on FPGA

CRC (Cyclic Redundancy Check) block was developed on FPGA (Field Programmable Gate Array) in order to meet the needs for simple, low-power and low-cost wireless communication such as Zigbee Zigbee operates primarily in the 24 GHz band, which makes the technology easily applicable and worldwide available This paper gives a short overview of CRC block in the digital transmitter based on Zigbee Standard The purpose of the research is to diversify the design methods by using the Verilog code entry through Xilinx ISE 82i Here, the simulation and measurement results are also presented to verify the functionality of the CRC block The data rate of CRC block is 250 kbps

Development of the CRC block for Zigbee Standard on FPGA

Security has become an important concern in wireless communication systems both for the users and the providers. Without a secure medium, users can have their transmissions eavesdropped or sensitive information tapped. Therefore, this paper focuses on the implementation of security algorithm, which is best embedded in the mobile devices. It is well known that most wireless communication standards implement an advanced encryption standard (AES) as a security algorithm. However, the AES is a complex algorithm that consumes a larger design core, time, and power source. Hence, a high-performance Blowfish algorithm is proposed and developed using a Zynq-7000 field-programmable gate array (FPGA). The performance is analyzed in terms of its architecture, throughput, and power consumption. Results show that the proposed Blowfish reduces slice usage by 63% and increases throughput by 29% at low power consumption.

Rafidah Ahmad

Papers

Development of an improved power-throughput Blowfish algorithm on FPGA

A Survey of High Performance Cryptography Algorithms for WiMAX Applications Using SDR

Implementation of IEEE 802.15.4-based OQPSK-pulse-shaping block on FPGA

Development of the CRC block for Zigbee Standard on FPGA

Implementation of a High-Performance Blowfish for Secure Wireless Communication