Cuckoo search (CS) was introduced by Xin-She Yang and Suash Deb in 2009, and it has attracted great attention due to its promising efficiency in solving many optimization problems and real-world applications. In the last few years, many papers have been published regarding cuckoo search, and the relevant literature has expanded significantly. This chapter summarizes briefly the majority of the literature about cuckoo search in peer-reviewed journals and conferences found so far. These references can be systematically classified into appropriate categories, which can be used as a basis for further research.

Cuckoo Search: A Brief Literature Review

Cuckoo Search (CS) algorithm is nature inspired global optimization algorithm based on the brood parasitic behavior of cuckoos. It has proved to be an efficient algorithm as it has been successfully applied to solve a large number of problems of different areas. CS employs Levy flights to generate step size and to search the solution space effectively. The local search is carried out using switch probability in which certain percentages of solutions are removed. Though CS is an effective algorithm, still its performance can be improved by incorporating the exploration and exploitation during the search process. In this work, three modified versions of CS are proposed to improve the properties of exploration and exploitation. All these versions employ Cauchy operator to generate the step size instead of Levy flights to efficiently explore the search space. Moreover, two new concepts, division of population and division of generations, are also introduced in CS so as to balance the exploration and exploitation. The proposed versions of CS are tested on 24 standard benchmark problems with different dimension sizes and varying population sizes and the effect of probability switch has been studied. Apart from this, the best of the proposed versions is also tested on CEC 2015 benchmark suite. The modified algorithms have been statistically tested in comparison to the state-of-the-art algorithms, namely grey wolf optimization (GWO), differential evolution (DE), firefly algorithm (FA), flower pollination algorithm (FPA) and bat algorithm (BA). The numerical and statistical results prove the superiority of the proposed versions with respect to other popular algorithms available in the literature.

New cuckoo search algorithms with enhanced exploration and exploitation properties

http://cyberleninka.ru/article/n/shkola-proektirovaniya-svch-ustroystv-v-cst-studio-suite.pdf

Школа проектирования СВч устройств в cst Studio suite

Cuckoo search (CS) is an efficient swarm-intelligence-based algorithm and significant developments have been made since its introduction in 2009. CS has many advantages due to its simplicity and efficiency in solving highly non-linear optimisation problems with real-world engineering applications. This paper provides a timely review of all the state-of-the-art developments in the last five years, including the discussions of theoretical background and research directions for future development of this powerful algorithm.

A comprehensive review of cuckoo search: variants and hybrids

The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

A Review on Power Supply Induced Jitter

The Power Integrity problem for high speed systems is discussed in context of selection and placement of decoupling capacitors. Power Integrity is maintained by damping the cavity mode peaks at resonant frequencies using decoupling capacitors. This article focuses on damping cavity mode effects in power delivery networks by the particle swarm optimization technique. The s-parameter data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their locations on the board are found using the presented methodology, which can be used for similar power delivery networks in high speed systems.

Selection and placement of decoupling capacitors in high speed systems

With the advancement of VLSI technology, the effect of jitter is becoming more critical on high speed signals. To negate the effect of jitter on these signals, the causes of jitter in a circuit need to be identified by decomposing the jitter. In this paper, a comparative analysis of various jitter estimation techniques is presented. The statistical domain methods are based on fitting techniques while the frequency domain methods are based on frequency spectrum analysis. This work describes both statistical domain methods and frequency domain methods. Further, their strengths and limitations are discussed. The algorithms are implemented in MATLAB and the results are extensively verified with Agilent ADS.

A comparative analysis of jitter estimation techniques

Integrated System Level Simulations of high speed serial links are necessary for the channel reliability and robustness. Increasing data rates and sharp transition time require high bandwidth systems. System level simulation are required to optimize channel design keeping cost of implementation at moderate or low level while meeting system level channel Bit Error Rate requirement for high bandwidth systems. The parameters which influence the channel and it's interconnect environment are primarily governed by signal integrity and power integrity requirements. In this paper, System Level Robustness Analysis of High Speed Serial Links is demonstrated with external environment considerations taken into account. A strong correlation between measured and simulated results is shown. A generic methodology for high speed serial links is presented with complete analysis of package, board, termination, Signal Quality inrush Droop/Drop (SQiDD), decoupling network etc. I. INTRODUCTION In Semiconductor industry due to tool limitations package analysis, board analysis, mixed signal simulations are performed separately. The complete channel performance is cumulative effect of whole interconnect environment consisting of transceiver, bond wire, package substrate, board, media/cable and termination environment. 'On-the- Board System' means die, package and board integrated together, to form a complete system. There is always a trade off between the various entities which form part of channel environment. In high speed transceivers, Signal Integrity (SI) and Power Integrity (PI) are the most important factors for the designers to keep in the mind while designing a system, as it affects the reliability of transmission at high data rates. This paper presents a Generic Flow for complete On-the- Board System Level Simulation to simulate and analyze the Reliability and Robustness of any PHY ( with example of USB 2.0 PHY), in context of high speed data transmission. Three advantages of SI and PI Analysis are: 1) This analysis is useful to perceive the behavior of whole system at simulation level accurately. 2) This can be used to ensure the Robustness and Reliability of a channel for the targeted bit error rate. 3) It will help the designers to modify the system before it is fabricated. Thus it will reduce product cost and minimize silicon iterations. II. SIGNAL AND POWER INTEGRITY AT SYSTEM LEVEL Signal Integrity means to preserve the signal as it propagates through the media between the transmitter and the receiver (i.e. without distortion in its amplitude shape and jitter performance). At higher speeds, board traces and package signal nets behave like transmission lines. In Serial Links (at system level), there are many types of losses/reflections that may cause distortion in signal quality e.g. reflection loss, insertion loss, coupling etc. Power Integrity (PI) deals with the power delivery network from a voltage source to active devices (ICs) through boards and packages. The noise in the power distribution network mainly affects the system jitter performance as jitter originates from the varying propagation delay caused by shifting bias levels in active circuits. This phenomenon is more prominent with shrinking technologies. Together this environment causes degradation in signal quality which can be primarily measured either by eye diagram or quantitatively by system Bit error rate.

Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links

Swarm intelligence is applied to a module of high speed system design problem. To maintain power integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances' peaks is presented. The optimal values and the optimal positions of the decoupling capacitors are found using three different swarm intelligence methods - particle swarm optimization, cuckoo search method and firefly algorithm. Optimum values and locations of decoupling capacitors are obtained, by which anti-resonances' peaks of loaded board are minimized.

Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms

System-level signal integrity (SI) and power integrity (PI) problems are taken into account. System-level simulation of high-speed systems with effect of external environment is described. SI and PI issues with complete analysis of package, board, termination, squid card, and decoupling network are shown. Common problems of simulations-passivity violation, stability, causality, and interoperability, are also discussed.

Raj Kumar Nagpal

Papers

Selection and placement of decoupling capacitors in high speed systems

A comparative analysis of jitter estimation techniques

Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links

Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms

Signal Integrity and Power Integrity Issues at System Level