Showing papers by "Rakesh Malik published in 2016"

An analysis of power supply induced jitter for a voltage mode driver in high speed serial links

Abstract: Estimation of jitter in early design cycle of an SoC is necessary to avoid jitter budget conflicts in the design. In this paper, an analysis of power supply induced jitter in a commonly used voltage mode driver architecture in serial links is discussed. The circuit used for the analysis is designed in 28nm FD-SOI technology but the analysis is technology independent. Jitter induced by noise in power delivery networks is analyzed by a transfer function from power supply to the output by a small signal equivalent model. The analysis can be extended generically for System-On-Chip (SoC) level design considerations.

A 0.065mm 2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB

Abstract: Most of the high speed low power ADCs are interleaved using calibration which have some drawback like calibration time, the complexity associated with calibration algorithm and its circuit implementation. Therefore a single channel calibration-free 12-bit ADC sampling at 600MS/s in 28nm UTBB FDSOI is presented. Selected ADC architecture of mixing Pipelined stage and Asynchronous SAR demonstrates advantages and suitability of different design techniques utilizing forward body bias (FBB) capability available for FDSOI CMOS. Measured silicon results show >9dB performance improvement with FBB voltage range of 0–1.8V. Integrated body bias generator (BBGEN) ensures required voltages for FBB. This work measures the 60.7dB SINAD at Nyquist frequency achieving Walden FOM of 37.2fJ/conv-step and Schreier FOM of 162.5dB at 600MS/s. It is also achieving 57dB SINAD at 800Ms/s, >50dB SINAD up to 950MS/s and 58.5dB SINAD till 500Mhz input frequency.

Baseband OFDM physical layer implementation on FPGA using SystemVue

Abstract: OFDM (Orthogonal Frequency Division Multiplexing) technique is a multicarrier modulation technique in which data bits are transmitted in parallel over multiple subcarriers. Its main advantage to other techniques lies in its robustness against multipath fading and ISI (Inter Symbol Interference). It has widely gained acceptance and is the integral part of modern high speed systems like Wi-Fi (802.11a), LTE (Long Term evolution), DMT (Discrete Multi-tone Technique) systems, DVB (Digital Video Broadcast) systems. OFDM physical layer is also used for SDR (Software Defined Radio) based applications. In this paper a fast prototype design from concept to implementation of an OFDM system is carried out using Keysight Technologies Tool ‘SYSTEMVUE’. The implementation of final design was done in 40 nm CMOS Xilinx Virtex VI XC6VLX760 FPGA. The results obtained were analyzed on LA (Logic Analyzer) and were verified with the simulation results. Using SystemVue's model based FPGA flow rapid prototyping and high gain in design time can be achieved.

Parallel pipeline logic circuit for generating CRC values utilizing lookup table

Abstract: CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.