R
Rakesh Malik
Researcher at STMicroelectronics
Publications - 51
Citations - 329
Rakesh Malik is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Power integrity & Jitter. The author has an hindex of 9, co-authored 51 publications receiving 266 citations.
Papers
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Journal ArticleDOI
Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)
TL;DR: In this paper, an efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented, based on separating the large signal response and the small signal noise response and subsequently combining the results.
Proceedings ArticleDOI
Minimizing core supply noise in a power delivery network by optimization of decoupling capacitors using simulated annealing
TL;DR: In this paper, an optimal decoupling network is designed by Simulated Annealing to reduce the power supply noise in power delivery networks, which reduces the cumulative impedance of power delivery network.
Proceedings ArticleDOI
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process
TL;DR: This paper describes a novel low power 10-bit 125 Msps pipelined ADC implemented in 65 nm standard digital CMOS process that employs novel techniques of adaptive biasing and cross coupled compensation to achieve improved settling behavior with significant power efficiency.
Journal ArticleDOI
Selection and placement of decoupling capacitors in high speed systems
Jai Narayan Tripathi,Jayanta Mukherjee,Prakash R. Apte,Nitin Kumar Chhabra,Raj Kumar Nagpal,Rakesh Malik +5 more
TL;DR: In this paper, the authors focus on damping cavity mode effects in power delivery networks by the particle swarm optimization technique and find the optimal capacitors and their locations on the board using the presented methodology.
Patent
Adaptive delay based asynchronous successive approximation analog-to-digital converter
TL;DR: In this article, an asynchronous SAR ADC is proposed to convert an analog signal into a series of digital pulses in an efficient, low power manner, where instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner.