Statistical Methods For Agricultural Workers

Cuckoo search (CS) was introduced by Xin-She Yang and Suash Deb in 2009, and it has attracted great attention due to its promising efficiency in solving many optimization problems and real-world applications. In the last few years, many papers have been published regarding cuckoo search, and the relevant literature has expanded significantly. This chapter summarizes briefly the majority of the literature about cuckoo search in peer-reviewed journals and conferences found so far. These references can be systematically classified into appropriate categories, which can be used as a basis for further research.

Cuckoo Search: A Brief Literature Review

Provided is a video coding method and a video decoding method increasing the resolution and quality of images while suppressing an amount of data required for increasing the resolution. A video coding apparatus includes a first orthogonal transformation unit performing discrete cosine transform on an input picture signal, a low-pass filter performing low-pass filtering on the input picture signal, a downsampling unit downsampling the resolution of a low-frequency image signal, a coding unit compressing and coding a reduced image signal, a local decoding unit decoding a coded bit stream, a second orthogonal transformation unit performing discrete cosine transform on a decoded image signal, and a modification information generation unit generating, based on input image DCT coefficients and decoded image DCT coefficients, coefficient modification information used for modifying orthogonal transformation coefficients obtained by performing orthogonal transformation on a decoded video signal obtained from a coded bit stream.

Video encoding method and video decoding method

Cuckoo Search (CS) algorithm is nature inspired global optimization algorithm based on the brood parasitic behavior of cuckoos. It has proved to be an efficient algorithm as it has been successfully applied to solve a large number of problems of different areas. CS employs Levy flights to generate step size and to search the solution space effectively. The local search is carried out using switch probability in which certain percentages of solutions are removed. Though CS is an effective algorithm, still its performance can be improved by incorporating the exploration and exploitation during the search process. In this work, three modified versions of CS are proposed to improve the properties of exploration and exploitation. All these versions employ Cauchy operator to generate the step size instead of Levy flights to efficiently explore the search space. Moreover, two new concepts, division of population and division of generations, are also introduced in CS so as to balance the exploration and exploitation. The proposed versions of CS are tested on 24 standard benchmark problems with different dimension sizes and varying population sizes and the effect of probability switch has been studied. Apart from this, the best of the proposed versions is also tested on CEC 2015 benchmark suite. The modified algorithms have been statistically tested in comparison to the state-of-the-art algorithms, namely grey wolf optimization (GWO), differential evolution (DE), firefly algorithm (FA), flower pollination algorithm (FPA) and bat algorithm (BA). The numerical and statistical results prove the superiority of the proposed versions with respect to other popular algorithms available in the literature.

New cuckoo search algorithms with enhanced exploration and exploitation properties

In digital video image encoding and decoding, a filter type is selected based on symmetrical properties of the images and coefficient values of an interpolation filter are calculated based on the selected filter type. Coefficient values, filter tap-length and selected filter-type are provided in the encoded video data. Coefficient values are also calculated based on a prediction signal representative of the different between a video frame and a reference image. The prediction signal is calculated from the reference image based on a predefined base filter and motion estimation performed on the video frame. The predefined base filter has fixed coefficient values. Coefficient values are selected from interpolation of pixel values in a selected image segment in the video frame. Symmetry properties of images can be a vertical symmetry, a horizontal symmetry and a combination thereof, so that only a portion of the filter coefficients are coded.

Adaptive interpolation filters for video coding

An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed methods are validated on several examples of voltage-mode driver circuits, designed in different technologies and in the presence of different types of noise sources.

Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)

An efficient methodology for minimizing core supply noise in Power Delivery Networks is presented. To reduce the power supply noise, an optimal decoupling network is designed by Simulated Annealing. The cumulative impedance of Power Delivery Network is reduced using lesser number of decoupling capacitors compared to placing decoupling capacitors intuitively. The supply noise is minimized according to the requirement of system specifications and the corresponding jitter reduction is reported.

Minimizing core supply noise in a power delivery network by optimization of decoupling capacitors using simulated annealing

This paper describes a novel low power 10-bit 125 Msps pipelined ADC implemented in 65 nm standard digital CMOS process. Proposed ADC implements 2.5 b/stage with amplifier shared between consecutive stages, achieves best in class FOM of 0.27 pJ/step with conversion power of 0.16 mW/Msps. The ADC amplifier employs novel techniques of adaptive biasing and cross coupled compensation to achieve improved settling behavior with significant power efficiency. This ADC occupies 0.13mm area and achieves maximum 0.3 LSB DNL and 0.6 LSB INL along with 9.26 ENOB at 125 Msps dissipating 20 mW power from 1.2v supply.

20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process

The Power Integrity problem for high speed systems is discussed in context of selection and placement of decoupling capacitors. Power Integrity is maintained by damping the cavity mode peaks at resonant frequencies using decoupling capacitors. This article focuses on damping cavity mode effects in power delivery networks by the particle swarm optimization technique. The s-parameter data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their locations on the board are found using the presented methodology, which can be used for similar power delivery networks in high speed systems.

Selection and placement of decoupling capacitors in high speed systems

An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

Rakesh Malik

Papers

Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)

Minimizing core supply noise in a power delivery network by optimization of decoupling capacitors using simulated annealing

20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process

Selection and placement of decoupling capacitors in high speed systems

Adaptive delay based asynchronous successive approximation analog-to-digital converter