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Rakesh Malik

Researcher at STMicroelectronics

Publications -  51
Citations -  329

Rakesh Malik is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Power integrity & Jitter. The author has an hindex of 9, co-authored 51 publications receiving 266 citations.

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Patent

Parallel pipeline logic circuit for generating CRC values utilizing lookup table

TL;DR: In this article, the N exclusive-OR gates are used to generate a final N-bit CRC value for the M-bit data frame, which is then used to calculate the position of the bit in the data frame.
Proceedings ArticleDOI

Application of nature inspired algorithms in power delivery network design: An industrial case study

TL;DR: Three natural computing algorithms - Particle Swarm Optimization, Cuckoo Search and Firefly Algorithm are used and compared for solving an industrial problem of power delivery network design.
Proceedings ArticleDOI

The harmonics impact study of a DC-DC buck converter through a power delivery network

TL;DR: In this article, a nonlinear distortion analysis of power delivery network and the impact of nonlinear characteristics of DC-DC converter on the PDN output have been analyzed The harmonic components for an equivalent PDN model have been estimated using Volterra series for 50 Hz input ripples.
Proceedings ArticleDOI

Estimation of inter-symbol interference using clock pattern

TL;DR: An efficient methodology for estimation of inter-symbol interference using clock pattern is described and a brief overview of other jitter components segregation techniques are introduced.
Proceedings ArticleDOI

Modelling and Analysis of Power-Ground Plane for High Speed VLSI System

TL;DR: In this article, the authors presented a RLC equivalent model of power plane for power distribution network (PDN) in high speed VLSI system consisting of package, board, and voltage regulator module.